The static scheduling may prevent some interrupt requests from being serviced. To avoid this, the CPUINT offers round robin scheduling for normal-priority (LVL0) interrupts. In the round robin scheduling, the CPUINT.LVL0PRI register stores the last acknowledged interrupt vector number. This register ensures that the last acknowledged interrupt vector gets the lowest priority and is automatically updated by the hardware. The following figure illustrates the priority order after acknowledging IVEC Y and after acknowledging IVEC Y+1.
The round robin scheduling for LVL0 interrupt requests is enabled by writing a
‘1’ to the Round Robin Priority Enable (LVL0RR) bit in the Control A
(CPUINT.CTRLA) register.