Interrupt Flag Register - Normal Mode

Name:
INTFLAGS
Offset:
0x0B
Reset:
0x00
Access:
-
Bit76543210
CMP2CMP1CMP0OVF
AccessR/WR/WR/WR/W
Reset0000

Bit 6 – CMP2: Compare Channel 2 Interrupt Flag

Compare Channel 2 Interrupt Flag

See the CMP0 flag description.

Bit 5 – CMP1: Compare Channel 1 Interrupt Flag

Compare Channel 1 Interrupt Flag

See the CMP0 flag description.

Bit 4 – CMP0: Compare Channel 0 Interrupt Flag

Compare Channel 0 Interrupt Flag

The Compare Interrupt (CMPn) flag is set on a compare match on the corresponding compare channel.

For all modes of operation, the CMPn flag will be set when a compare match occurs between the Count (TCAn.CNT) register and the corresponding Compare n (TCAn.CMPn) register. The CMPn flag is not cleared automatically. It will be cleared only by writing a ‘1’ to its bit location.

Bit 0 – OVF: Overflow/Underflow Interrupt Flag

Overflow/Underflow Interrupt Flag

This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the WGMODE setting. The OVF flag is not cleared automatically. It will be cleared only by writing a ‘1’ to its bit location.