Register Summary
Offset
Name
Bit Pos.
7
6
5
4
3
2
1
0
0x00
CTRLA
7:0
IVSEL
CVT
LVL0RR
0x01
STATUS
7:0
NMIEX
LVL1EX
LVL0EX
0x02
LVL0PRI
7:0
LVL0PRI[7:0]
0x03
LVL1VEC
7:0
LVL1VEC[7:0]
Parent topic:
CPUINT - CPU Interrupt Controller