Contents
Introduction
megaAVR 0-series Overview
2.1. Memory Overview
2.2. Peripheral Overview
Features
4. Silicon Errata and Data Sheet Clarification Document
5. Block Diagram
6. Pinout
6.1. 28-Pin SSOP
6.2. 32-Pin VQFN/TQFP
6.3. 40-Pin PDIP
6.4. 48-Pin VQFN/TQFPreplace UQFN/-phrase with VQFN/ - no conditions, mind you - once we have a date code
7. I/O Multiplexing and Considerations
7.1. Multiplexed Signals
8. Conventions
8.1. Numerical Notation
8.2. Memory Size and Type
8.3. Frequency and Time
8.4. Registers and Bits
8.4.1. Addressing Registers from Header Files
8.5. ADC Parameter Definitions
9. AVR CPU
9.1. Features
9.2. Overview
9.3. Architecture
9.4. Arithmetic Logic Unit (ALU)
9.4.1. Hardware Multiplier
9.5. Functional Description
9.5.1. Program Flow
9.5.2. Instruction Execution Timing
9.5.3. Status Register
9.5.4. Stack and Stack Pointer
9.5.5. Register File
9.5.5.1. The X-, Y-, and Z-Registers
9.5.6. Accessing 16-Bit Registers
9.5.7. Configuration Change Protection (CCP)
9.5.7.1. Sequence for Write Operation to Configuration Change Protected I/O Registers
9.5.7.2. Sequence for Execution of Self-Programming
9.5.8. On-Chip Debug Capabilities
9.6. Register Summary
9.7. Register Description
9.7.1. CCP
9.7.2. SP
9.7.3. SREG
10. Memories
10.1. Overview
10.2. Memory Map
10.3. In-System Reprogrammable Flash Program Memory
10.4. SRAM Data Memory
10.5. EEPROM Data Memory
10.6. User Row (USERROW)
10.7. Signature Row (SIGROW)
10.7.1. Signature Row Summary
10.7.2. Signature Row Description
10.7.2.1. Device ID n
10.7.2.2. Serial Number Byte n
10.7.2.3. OSC16 Calibration byte
10.7.2.4. OSC16 Temperature Calibration byte
10.7.2.5. OSC20 Calibration byte
10.7.2.6. OSC20 Temperature Calibration byte
10.7.2.7. Temperature Sensor Calibration n
10.7.2.8. OSC16 Error at 3V
10.7.2.9. OSC16 Error at 5V
10.7.2.10. OSC20 Error at 3V
10.7.2.11. OSC20 Error at 5V
10.8. Fuses (FUSE)
10.8.1. Fuse Summary - FUSE
10.8.2. Fuse Description
10.8.2.1. Watchdog Configuration
10.8.2.2. BOD Configuration
10.8.2.3. Oscillator Configuration
10.8.2.4. System Configuration 0
10.8.2.5. System Configuration 1
10.8.2.6. Application Code End
10.8.2.7. Boot End
10.8.2.8. Lockbits
10.9. Memory Section Access from CPU and UPDI on Locked Device
10.10. I/O Memory
10.10.1. Register Summary
10.10.2. Register Description
10.10.2.1. General Purpose I/O Register n
11. Peripherals and Architecture
11.1. Peripheral Module Address Map
11.2. Interrupt Vector Mapping
11.3. SYSCFG - System Configuration
11.3.1. Register Summary
11.3.2. Register Description
11.3.2.1. Device Revision ID Register
12. NVMCTRL - Nonvolatile Memory Controller
12.1. Features
12.2. Overview
12.2.1. Block Diagram
12.3. Functional Description
12.3.1. Memory Organization
12.3.1.1. Flash
12.3.1.2. EEPROM
12.3.1.3. User Row
12.3.2. Memory Access
12.3.2.1. Read
12.3.2.2. Page Buffer Load
12.3.2.3. Programming
12.3.2.4. Commands
12.3.2.4.1. Write Page Command
12.3.2.4.2. Erase Page Command
12.3.2.4.3. Erase/Write Page Command
12.3.2.4.4. Page Buffer Clear Command
12.3.2.4.5. Chip Erase Command
12.3.2.4.6. EEPROM Erase Command
12.3.2.4.7. Write Fuse Command
12.3.2.5. Write Access after Reset
12.3.3. Preventing Flash/EEPROM Corruption
12.3.4. Interrupts
12.3.5. Sleep Mode Operation
12.3.6. Configuration Change Protection
12.4. Register Summary
12.5. Register Description
12.5.1. Control A
12.5.2. Control B
12.5.3. Status
12.5.4. Interrupt Control
12.5.5. Interrupt Flags
12.5.6. Data
12.5.7. Address
13. CLKCTRL - Clock Controller
13.1. Features
13.2. Overview
13.2.1. Block Diagram - CLKCTRL
13.2.2. Signal Description
13.3. Functional Description
13.3.1. Sleep Mode Operation
13.3.2. Main Clock Selection and Prescaler
13.3.3. Main Clock After Reset
13.3.4. Clock Sources
13.3.4.1. Internal Oscillators
13.3.4.1.1. 16/20 MHz Oscillator (OSC20M)
13.3.4.1.1.1. OSC20M Stored Frequency Error Compensation
13.3.4.1.2. 32.768 kHz Oscillator (OSCULP32K)
13.3.4.2. External Clock Sources
13.3.4.2.1. 32.768 kHz Crystal Oscillator (XOSC32K)
13.3.4.2.2. External Clock (EXTCLK)
13.3.5. Configuration Change Protection
13.4. Register Summary
13.5. Register Description
13.5.1. Main Clock Control A
13.5.2. Main Clock Control B
13.5.3. Main Clock Lock
13.5.4. Main Clock Status
13.5.5. 16/20 MHz Oscillator Control A
13.5.6. 16/20 MHz Oscillator Calibration A
13.5.7. 16/20 MHz Oscillator Calibration B
13.5.8. 32.768 kHz Oscillator Control A
13.5.9. 32.768 kHz Crystal Oscillator Control A
14. SLPCTRL - Sleep Controller
14.1. Features
14.2. Overview
14.2.1. Block Diagram
14.3. Functional Description
14.3.1. Initialization
14.3.2. Operation
14.3.2.1. Sleep Modes
14.3.2.2. Wake-up Time
14.3.3. Debug Operation
14.4. Register Summary
14.5. Register Description
14.5.1. Control A
15. RSTCTRL - Reset Controller
15.1. Features
15.2. Overview
15.2.1. Block Diagram
15.2.2. Signal Description
15.3. Functional Description
15.3.1. Initialization
15.3.2. Operation
15.3.2.1. Reset Sources
15.3.2.1.1. Power-on Reset (POR)
15.3.2.1.2. Brown-out Detector (BOD) Reset
15.3.2.1.3. External Reset
15.3.2.1.4. Watchdog Reset
15.3.2.1.5. Software Reset
15.3.2.1.6. Unified Program and Debug Interface (UPDI) Reset
15.3.2.1.7. Domains Affected By Reset
15.3.2.2. Reset Time
15.3.3. Sleep Mode Operation
15.3.4. Configuration Change Protection
15.4. Register Summary
15.5. Register Description
15.5.1. Reset Flag Register
15.5.2. Software Reset Register
16. CPUINT - CPU Interrupt Controller
16.1. Features
16.2. Overview
16.2.1. Block Diagram
16.3. Functional Description
16.3.1. Initialization
16.3.2. Operation
16.3.2.1. Enabling, Disabling and Resetting
16.3.2.2. Interrupt Vector Locations
16.3.2.3. Interrupt Response Time
16.3.2.4. Interrupt Priority
16.3.2.4.1. Non-Maskable Interrupts
16.3.2.4.2. High-Priority Interrupt
16.3.2.4.3. Normal-Priority Interrupts
16.3.2.4.3.1. Static Scheduling
16.3.2.4.3.2. Modified Static Scheduling
16.3.2.4.3.3. Round Robin Scheduling
16.3.2.5. Compact Vector Table
16.3.3. Debug Operation
16.3.4. Configuration Change Protection
16.4. Register Summary
16.5. Register Description
16.5.1. Control A
16.5.2. Status
16.5.3. Interrupt Priority Level 0
16.5.4. Interrupt Vector with Priority Level 1
17. EVSYS - Event System
17.1. Features
17.2. Overview
17.2.1. Block Diagram
17.2.2. Signal Description
17.3. Functional Description
17.3.1. Initialization
17.3.2. Operation
17.3.2.1. Event User Multiplexer Setup
17.3.2.2. Event System Channel
17.3.2.3. Event Generators
17.3.2.4. Event Users
17.3.2.5. Synchronization
17.3.2.6. Software Event
17.3.3. Sleep Mode Operation
17.3.4. Debug Operation
17.4. Register Summary
17.5. Register Description
17.5.1. Channel Strobe
17.5.2. Channel n Generator Selection
17.5.3. User Channel Mux
18. PORTMUX - Port Multiplexer
18.1. Overview
18.2. Register Summary - PORTMUX
18.3. Register Description
18.3.1. PORTMUX Control for Event System
18.3.2. PORTMUX Control for CCL
18.3.3. PORTMUX Control for USART
18.3.4. PORTMUX Control for TWI and SPI
18.3.5. PORTMUX Control for TCA
18.3.6. PORTMUX Control for TCB
19. PORT - I/O Pin Configuration
19.1. Features
19.2. Overview
19.2.1. Block Diagram
19.2.2. Signal Description
19.3. Functional Description
19.3.1. Initialization
19.3.2. Operation
19.3.2.1. Basic Functions
19.3.2.2. Port Configuration
19.3.2.3. Pin Configuration
19.3.2.4. Virtual Ports
19.3.2.5. Peripheral Override
19.3.3. Interrupts
19.3.3.1. Asynchronous Sensing Pin Properties
19.3.4. Events
19.3.5. Sleep Mode Operation
19.3.6. Debug Operation
19.4. Register Summary - PORTx
19.5. Register Description - PORTx
19.5.1. Data Direction
19.5.2. Data Direction Set
19.5.3. Data Direction Clear
19.5.4. Data Direction Toggle
19.5.5. Output Value
19.5.6. Output Value Set
19.5.7. Output Value Clear
19.5.8. Output Value Toggle
19.5.9. Input Value
19.5.10. Interrupt Flags
19.5.11. Port Control
19.5.12. Pin n Control
19.6. Register Summary - VPORTx
19.7. Register Description - VPORTx
19.7.1. Data Direction
19.7.2. Output Value
19.7.3. Input Value
19.7.4. Interrupt Flags
20. BOD - Brown-out Detector
20.1. Features
20.2. Overview
20.2.1. Block Diagram
20.3. Functional Description
20.3.1. Initialization
20.3.2. Interrupts
20.3.3. Sleep Mode Operation
20.3.4. Configuration Change Protection
20.4. Register Summary
20.5. Register Description
20.5.1. Control A
20.5.2. Control B
20.5.3. VLM Control A
20.5.4. Interrupt Control
20.5.5. VLM Interrupt Flags
20.5.6. VLM Status
21. VREF - Voltage Reference
21.1. Features
21.2. Overview
21.2.1. Block Diagram
21.3. Functional Description
21.3.1. Initialization
21.4. Register Summary - VREF
21.5. Register Description
21.5.1. Control A
21.5.2. Control B
22. WDT - Watchdog Timer
22.1. Features
22.2. Overview
22.2.1. Block Diagram
22.2.2. Signal Description
22.3. Functional Description
22.3.1. Initialization
22.3.2. Clocks
22.3.3. Operation
22.3.3.1. Normal Mode
22.3.3.2. Window Mode
22.3.3.3. Configuration Protection and Lock
22.3.4. Sleep Mode Operation
22.3.5. Debug Operation
22.3.6. Synchronization
22.3.7. Configuration Change Protection
22.4. Register Summary - WDT
22.5. Register Description
22.5.1. Control A
22.5.2. Status
23. TCA - 16-bit Timer/Counter Type A
23.1. Features
23.2. Overview
23.2.1. Block Diagram
23.2.2. Signal Description
23.3. Functional Description
23.3.1. Definitions
23.3.2. Initialization
23.3.3. Operation
23.3.3.1. Normal Operation
23.3.3.2. Double Buffering
23.3.3.3. Changing the Period
23.3.3.4. Compare Channel
23.3.3.4.1. Waveform Generation
23.3.3.4.2. Frequency (FRQ) Waveform Generation
23.3.3.4.3. Single-Slope PWM Generation
23.3.3.4.4. Dual-Slope PWM
23.3.3.4.5. Port Override for Waveform Generation
23.3.3.5. Timer/Counter Commands
23.3.3.6. Split Mode - Two 8-Bit Timer/Counters
23.3.4. Events
23.3.5. Interrupts
23.3.6. Sleep Mode Operation
23.4. Register Summary - Normal Mode
23.5. Register Description - Normal Mode
23.5.1. Control A - Normal Mode
23.5.2. Control B - Normal Mode
23.5.3. Control C - Normal Mode
23.5.4. Control D - Normal Mode
23.5.5. Control Register E Clear - Normal Mode
23.5.6. Control Register E Set - Normal Mode
23.5.7. Control Register F Clear
23.5.8. Control Register F Set
23.5.9. Event Control
23.5.10. Interrupt Control Register - Normal Mode
23.5.11. Interrupt Flag Register - Normal Mode
23.5.12. Debug Control Register - Normal Mode
23.5.13. Temporary Bits for 16-Bit Access
23.5.14. Counter Register - Normal Mode
23.5.15. Period Register - Normal Mode
23.5.16. Compare n Register - Normal Mode
23.5.17. Period Buffer Register
23.5.18. Compare n Buffer Register
23.6. Register Summary - Split Mode
23.7. Register Description - Split Mode
23.7.1. Control A - Split Mode
23.7.2. Control B - Split Mode
23.7.3. Control C - Split Mode
23.7.4. Control D - Split Mode
23.7.5. Control Register E Clear - Split Mode
23.7.6. Control Register E Set - Split Mode
23.7.7. Interrupt Control Register - Split Mode
23.7.8. Interrupt Flag Register - Split Mode
23.7.9. Debug Control Register - Split Mode
23.7.10. Low Byte Timer Counter Register - Split Mode
23.7.11. High Byte Timer Counter Register - Split Mode
23.7.12. Low Byte Timer Period Register - Split Mode
23.7.13. High Byte Period Register - Split Mode
23.7.14. Compare Register n For Low Byte Timer - Split Mode
23.7.15. High Byte Compare Register n - Split Mode
24. TCB - 16-Bit Timer/Counter Type B
24.1. Features
24.2. Overview
24.2.1. Block Diagram
24.2.2. Signal Description
24.3. Functional Description
24.3.1. Definitions
24.3.2. Initialization
24.3.3. Operation
24.3.3.1. Modes
24.3.3.1.1. Periodic Interrupt Mode
24.3.3.1.2. Time-Out Check Mode
24.3.3.1.3. Input Capture on Event Mode
24.3.3.1.4. Input Capture Frequency Measurement Mode
24.3.3.1.5. Input Capture Pulse-Width Measurement Mode
24.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode
24.3.3.1.7. Single-Shot Mode
24.3.3.1.8. 8-Bit PWM Mode
24.3.3.2. Output
24.3.3.3. Noise Canceler
24.3.3.4. Synchronized with Timer/Counter Type A
24.3.4. Events
24.3.5. Interrupts
24.3.6. Sleep Mode Operation
24.4. Register Summary
24.5. Register Description
24.5.1. Control A
24.5.2. Control B
24.5.3. Event Control
24.5.4. Interrupt Control
24.5.5. Interrupt Flags
24.5.6. Status
24.5.7. Debug Control
24.5.8. Temporary Value
24.5.9. Count
24.5.10. Capture/Compare
25. RTC - Real-Time Counter
25.1. Features
25.2. Overview
25.2.1. Block Diagram
25.3. Clocks
25.4. RTC Functional Description
25.4.1. Initialization
25.4.1.1. Configure the Clock CLK_RTC
25.4.1.2. Configure RTC
25.4.2. Operation - RTC
25.4.2.1. Enabling and Disabling
25.5. PIT Functional Description
25.5.1. Initialization
25.5.2. Operation - PIT
25.5.2.1. Enabling and Disabling
25.5.2.2. PIT Interrupt Timing
25.6. Crystal Error Correction
25.7. Events
25.8. Interrupts
25.9. Sleep Mode Operation
25.10. Synchronization
25.11. Debug Operation
25.12. Register Summary
25.13. Register Description
25.13.1. Control A
25.13.2. Status
25.13.3. Interrupt Control
25.13.4. Interrupt Flag
25.13.5. Temporary
25.13.6. Debug Control
25.13.7. Crystal Frequency Calibration
25.13.8. Clock Selection
25.13.9. Count
25.13.10. Period
25.13.11. Compare
25.13.12. Periodic Interrupt Timer Control A
25.13.13. Periodic Interrupt Timer Status
25.13.14. PIT Interrupt Control
25.13.15. PIT Interrupt Flag
25.13.16. Periodic Interrupt Timer Debug Control
26. USART - Universal Synchronous and Asynchronous Receiver and Transmitter
26.1. Features
26.2. Overview
26.2.1. Block Diagram
26.2.2. Signal Description
26.3. Functional Description
26.3.1. Initialization
26.3.2. Operation
26.3.2.1. Frame Formats
26.3.2.2. Clock Generation
26.3.2.2.1. The Fractional Baud Rate Generator
26.3.2.3. Data Transmission
26.3.2.3.1. Disabling the Transmitter
26.3.2.4. Data Reception
26.3.2.4.1. Receiver Error Flags
26.3.2.4.2. Disabling the Receiver
26.3.2.4.3. Flushing the Receive Buffer
26.3.3. Communication Modes
26.3.3.1. Synchronous Operation
26.3.3.1.1. Clock Operation
26.3.3.1.2. External Clock Limitations
26.3.3.1.3. USART in Host SPI Mode
26.3.3.1.3.1. Frame Formats
26.3.3.1.3.2. Clock Generation
26.3.3.1.3.3. Data Transmission
26.3.3.1.3.4. Data Reception
26.3.3.1.3.5. USART in Host SPI Mode vs. SPI
26.3.3.2. Asynchronous Operation
26.3.3.2.1. Clock Recovery
26.3.3.2.2. Data Recovery
26.3.3.2.3. Error Tolerance
26.3.3.2.4. Double-Speed Operation
26.3.3.2.5. Auto-Baud
26.3.3.2.6. Half-Duplex Operation
26.3.3.2.6.1. One-Wire Mode
26.3.3.2.6.2. RS-485 Mode
26.3.3.2.7. IRCOM Mode of Operation
26.3.4. Additional Features
26.3.4.1. Parity
26.3.4.2. Start-of-Frame Detection
26.3.4.3. Multiprocessor Communication
26.3.4.3.1. Using Multiprocessor Communication
26.3.5. Events
26.3.6. Interrupts
26.4. Register Summary
26.5. Register Description
26.5.1. Receiver Data Register Low Byte
26.5.2. Receiver Data Register High Byte
26.5.3. Transmit Data Register Low Byte
26.5.4. Transmit Data Register High Byte
26.5.5. USART Status Register
26.5.6. Control A
26.5.7. Control B
26.5.8. Control C - Normal Mode
26.5.9. Control C - Host SPI Mode
26.5.10. Baud Register
26.5.11. Control D
26.5.12. Debug Control Register
26.5.13. IrDA Control Register
26.5.14. IRCOM Transmitter Pulse Length Control Register
26.5.15. IRCOM Receiver Pulse Length Control Register
27. SPI - Serial Peripheral Interface
27.1. Features
27.2. Overview
27.2.1. Block Diagram
27.2.2. Signal Description
27.3. Functional Description
27.3.1. Initialization
27.3.2. Operation
27.3.2.1. Host Mode Operation
27.3.2.1.1. Normal Mode
27.3.2.1.2. Buffer Mode
27.3.2.1.3. SS Pin Functionality in Host Mode - Multi-Host Support
27.3.2.2. Client Mode
27.3.2.2.1. Normal Mode
27.3.2.2.2. Buffer Mode
27.3.2.2.3. SS Pin Functionality in Client Mode
27.3.2.3. Data Modes
27.3.2.4. Events
27.3.2.5. Interrupts
27.4. Register Summary
27.5. Register Description
27.5.1. Control A
27.5.2. Control B
27.5.3. Interrupt Control
27.5.4. Interrupt Flags - Normal Mode
27.5.5. Interrupt Flags - Buffer Mode
27.5.6. Data
28. TWI - Two-Wire Interface
28.1. Features
28.2. Overview
28.2.1. Block Diagram
28.2.2. Signal Description
28.3. Functional Description
28.3.1. General TWI Bus Concepts
28.3.2. TWI Basic Operation
28.3.2.1. Initialization
28.3.2.1.1. Host Initialization
28.3.2.1.2. Client Initialization
28.3.2.2. TWI Host Operation
28.3.2.2.1. Clock Generation
28.3.2.2.2. TWI Bus State Logic
28.3.2.2.3. Transmitting Address Packets
28.3.2.2.3.1. Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’
28.3.2.2.3.2. Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’
28.3.2.2.3.3. Case M3: Address Packet Transmit Complete - Address not Acknowledged by Client
28.3.2.2.3.4. Case M4: Arbitration Lost or Bus Error
28.3.2.2.4. Transmitting Data Packets
28.3.2.2.5. Receiving Data Packets
28.3.2.3. TWI Client Operation
28.3.2.3.1. Receiving Address Packets
28.3.2.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set to ‘0’
28.3.2.3.1.2. Case S2: Address Packet Accepted - Direction Bit Set to ‘1’
28.3.2.3.1.3. Case S3: Stop Condition Received
28.3.2.3.1.4. Case S4: Collision
28.3.2.3.2. Receiving Data Packets
28.3.2.3.3. Transmitting Data Packets
28.3.3. Additional Features
28.3.3.1. SMBus
28.3.3.2. Multi-Host
28.3.3.3. Smart Mode
28.3.3.4. Dual Mode
28.3.3.5. Quick Command Mode
28.3.3.6. 10-bit Address
28.3.4. Interrupts
28.3.5. Sleep Mode Operation
28.3.6. Debug Operation
28.4. Register Summary
28.5. Register Description
28.5.1. Control A
28.5.2. Dual Mode Control Configuration
28.5.3. Debug Control
28.5.4. Host Control A
28.5.5. Host Control B
28.5.6. Host Status
28.5.7. Host Baud Rate
28.5.8. Host Address
28.5.9. Host Data
28.5.10. Client Control A
28.5.11. Client Control B
28.5.12. Client Status
28.5.13. Client Address
28.5.14. Client Data
28.5.15. Client Address Mask
29. CRCSCAN - Cyclic Redundancy Check Memory Scan
29.1. Features
29.2. Overview
29.2.1. Block Diagram
29.3. Functional Description
29.3.1. Initialization
29.3.2. Operation
29.3.2.1. Checksum
29.3.3. Interrupts
29.3.4. Sleep Mode Operation
29.3.5. Debug Operation
29.4. Register Summary - CRCSCAN
29.5. Register Description
29.5.1. Control A
29.5.2. Control B
29.5.3. Status
30. CCL - Configurable Custom Logic
30.1. Features
30.2. Overview
30.2.1. Block Diagram
30.2.2. Signal Description
30.2.2.1. CCL Input Selection MUX
30.3. Functional Description
30.3.1. Operation
30.3.1.1. Enable-Protected Configuration
30.3.1.2. Enabling, Disabling, and Resetting
30.3.1.3. Truth Table Logic
30.3.1.4. Truth Table Inputs Selection
30.3.1.5. Filter
30.3.1.6. Edge Detector
30.3.1.7. Sequencer Logic
30.3.1.8. Clock Source Settings
30.3.2. Interrupts
30.3.3. Events
30.3.4. Sleep Mode Operation
30.4. Register Summary
30.5. Register Description
30.5.1. Control A
30.5.2. Sequencer Control 0
30.5.3. Sequencer Control 1
30.5.4. Interrupt Control 0
30.5.5. Interrupt Flag
30.5.6. LUT n Control A
30.5.7. LUT n Control B
30.5.8. LUT n Control C
30.5.9. TRUTHn
31. AC - Analog Comparator
31.1. Features
31.2. Overview
31.2.1. Block Diagram
31.2.2. Signal Description
31.3. Functional Description
31.3.1. Initialization
31.3.2. Operation
31.3.2.1. Input Hysteresis
31.3.2.2. Input Sources
31.3.2.2.1. Pin Inputs
31.3.2.2.2. Internal Inputs
31.3.2.3. Power Modes
31.3.2.4. Signal Compare and Interrupt
31.3.3. Events
31.3.4. Interrupts
31.3.5. Sleep Mode Operation
31.4. Register Summary
31.5. Register Description
31.5.1. Control A
31.5.2. MUX Control A
31.5.3. DAC Voltage Reference
31.5.4. Interrupt Control
31.5.5. Status
32. ADC - Analog-to-Digital Converter
32.1. Features
32.2. Overview
32.2.1. Block Diagram
32.2.2. Signal Description
32.3. Functional Description
32.3.1. Initialization
32.3.1.1. I/O Lines and Connections
32.3.2. Operation
32.3.2.1. Starting a Conversion
32.3.2.2. Clock Generation
32.3.2.3. Conversion Timing
32.3.2.4. Changing Channel or Reference Selection
32.3.2.4.1. ADC Input Channels
32.3.2.4.2. ADC Voltage Reference
32.3.2.4.3. Analog Input Circuitry
32.3.2.5. ADC Conversion Result
32.3.2.6. Temperature Measurement
32.3.2.7. Window Comparator Mode
32.3.3. Events
32.3.4. Interrupts
32.3.5. Sleep Mode Operation
32.4. Register Summary - ADCn
32.5. Register Description
32.5.1. Control A
32.5.2. Control B
32.5.3. Control C
32.5.4. Control D
32.5.5. Control E
32.5.6. Sample Control
32.5.7. MUXPOS
32.5.8. Command
32.5.9. Event Control
32.5.10. Interrupt Control
32.5.11. Interrupt Flags
32.5.12. Debug Run
32.5.13. Temporary
32.5.14. Result
32.5.15. Window Comparator Low Threshold
32.5.16. Window Comparator High Threshold
32.5.17. Calibration
33. UPDI - Unified Program and Debug Interface
33.1. Features
33.2. Overview
33.2.1. Block Diagram
33.2.2. Clocks
33.3. Functional Description
33.3.1. Principle of Operation
33.3.1.1. UPDI UART
33.3.1.2. BREAK Character
33.3.1.3. SYNCH Character
33.3.1.3.1. SYNCH in One-Wire Mode
33.3.2. Operation
33.3.2.1. UPDI Enable
33.3.2.2. UPDI Disable
33.3.2.3. UPDI Communication Error Handling
33.3.2.4. Direction Change
33.3.3. UPDI Instruction Set
33.3.3.1. LDS - Load Data from Data Space Using Direct Addressing
33.3.3.2. STS - Store Data to Data Space Using Direct Addressing
33.3.3.3. LD - Load Data from Data Space Using Indirect Addressing
33.3.3.4. ST - Store Data from UPDI to Data Space Using Indirect Addressing
33.3.3.5. LDCS - Load Data from Control and Status Register Space
33.3.3.6. STCS - Store Data to Control and Status Register Space
33.3.3.7. REPEAT - Set Instruction Repeat Counter
33.3.3.8. KEY - Set Activation Key or Send System Information Block
33.3.4. System Clock Measurement with UPDI
33.3.5. Interbyte Delay
33.3.6. System Information Block
33.3.7. Enabling of Key Protected Interfaces
33.3.7.1. Chip Erase
33.3.7.2. NVM Programming
33.3.7.3. User Row Programming
33.3.8. Events
33.3.9. Sleep Mode Operation
33.4. Register Summary
33.5. Register Description
33.5.1. Status A
33.5.2. Status B
33.5.3. Control A
33.5.4. Control B
33.5.5. ASI Key Status
33.5.6. ASI Key Status
33.5.7. ASI Reset Request
33.5.8. ASI Control A
33.5.9. ASI System Control A
33.5.10. ASI System Status
33.5.11. ASI CRC Status
34. Instruction Set Summary
35. Electrical Characteristics
35.1. Disclaimer
35.2. Absolute Maximum Ratings
35.3. General Operating Ratings
35.4. Power Considerations
35.5. Power Consumption
35.6. Wake-Up Time
35.7. Peripherals Power Consumption
35.8. BOD and POR Characteristics
35.9. External Reset Characteristics
35.10. Oscillators and Clocks
35.11. I/O Pin Characteristics
35.12. USART
35.13. SPI
35.14. TWI
35.15. VREF
35.16. ADC
35.16.1. Internal Reference Characteristics
35.16.2. External Reference Characteristics
35.17. TEMPSENSE
35.18. AC
35.19. UPDI
35.20. Programming Time
36. Typical Characteristics
36.1. Power Consumption
36.1.1. Supply Currents in Active Mode
36.1.2. Supply Currents in Idle Mode
36.1.3. Supply Currents in Power-Down Mode
36.1.4. Supply Currents in Standby Mode
36.1.5. Power-on Supply Currents
36.2. GPIO
36.3. VREF Characteristics
36.4. BOD Characteristics
36.5. ADC Characteristics
36.6. TEMPSENSE Characteristics
36.7. AC Characteristics
36.8. OSC20M Characteristics
36.9. OSCULP32K Characteristics
37. Ordering Information
38. Package Drawings
38.1. Package Marking Information
38.1.1. Package Marking Drawings
38.2. Online Package Drawings
38.3. 28-Pin SSOP
38.4. 32-Pin TQFP
38.5. 32-Pin VQFN
38.6. 32-Pin VQFN Wettable Flanks
38.7. 40-Pin PDIP
38.8. 48-Pin TQFP
38.9. 48-Pin VQFN
38.10. 48-Pin VQFN Wettable Flanks
39. Data Sheet Revision History
39.1. Rev. C - 02/2021
39.2. Rev. B - 06/2020
39.3. Rev.A - 01/2020
39.4. Appendix - Obsolete Revision History
39.4.1. Obsolete Publication Rev.C - 08/2019
39.4.2. Obsolete Publication Rev.B - 03/2019
39.4.3. Obsolete Publication Rev.A - 02/2018
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