| Device |
Writing the OSCLOCK Fuse in FUSE.OSCCFG to '1' Prevents Automatic Loading of Calibration Values |
X |
| ADC |
ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty Cycle |
X |
| One Extra Measurement Performed After Disabling ADC Free-Running Mode |
X |
| CCL |
The CCL Must be Disabled to Change the Configuration of a Single LUT |
X |
| NVMCTRL |
Wrong Reset Value of NVMCTRL.CTRLA Register |
X |
| TCA |
Restart Will Reset Counter Direction in NORMAL and FRQ Mode |
X |
| TCB |
Minimum Event Duration Must Exceed the Selected Clock Period |
X |
| The TCA Restart Command Does Not Force a Restart of TCB |
X |
| CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM Mode |
X |
| TCD |
Asynchronous Input Events Not Working When TCD Counter Prescaler is Used |
X |
| Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is ‘0’ or Dual Slope Mode is Used |
X |
| USART |
TXD Pin Override Not Released When Disabling the Transmitter |
X |
| Open-Drain Mode Does Not Work When TXD is Configured as Output |
X |
| Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode |
X |
| Receiver Non-Functional after Detection of Inconsistent Synchronization Field |
X |