The basic operation of USART is similar for both families, but the register and bit names are different. The AVR Dx devices have an improved register structure that allows a more efficient access to the configuration/status bits.
The following section details the mapping of ATmega128 registers into AVR Dx register structure (only ATmega registers and AVR Dx correspondences are figured):
| megaAVR® | AVR® Dx | Description |
|---|---|---|
| RXBn (UDRn read) | USARTn.RXDATAL | Receiver Data Register Low Byte |
| TXBn (UDRn write) | USARTn.TXDATAL | Transmit Data Register Low Byte |
| UCSRnB.RXB8n | USARTn.RXDATAH.DATA[8] | Receive Data Bit 8 |
| UCSRnB.TXB8n | USARTn.TXDATAH.DATA[8] | Transmit Data Bit 8 |
| UCSRnB.UCSZn[2] | USARTn.CTRLC.CHSIZE[2:0](1) | USART Character Size |
| UCSRnC.UCSZn[1:0] | ||
| UCSRnB.RXENn | USARTn.CTRLC.RXEN | Receiver Enable |
| UCSRnB.TXENn | USARTn.CTRLC.TXEN | Transmitter Enable |
| UCSRnB.RXCIENn | USARTn.CTRLA.RXCIE | RX Complete Interrupt Enable |
| UCSRnB.TXCIENn | USARTn.CTRLA.TXCIE | TX Complete Interrupt Enable |
| UCSRnB.UDRIENn | USARTn.CTRLA.DREIE | USART Data Register Empty Interrupt Enable |
| UCSRnA.RXCn | USART.STATUS.RXCIF | USART Receive Complete Flag |
| UCSRnA.TXCn | USART.STATUS.TXCIF | USART Transmit Complete Flag |
| UCSRnA.UDREn | USART.STATUS.DREIF | USART Data Register Empty Flag |
| UCSRnA.FEn | USARTn.RXDATAH.FERR | Framing Error |
| UCSRnA.DORn | USARTn.RXDATAH.BUFOVF | Data OverRun |
| UCSRnA.UPEn | USARTn.RXDATAH.PERR | Parity Error |
| UCSRnA.U2Xn | USARTn.CTRLB.RXMODE[1:0] = CLK2X | Double the USART operation Speed |
| UCSRnA.MPCMn | USARTn.CTRLB.MPCM | Multi-Processor Communication mode |
| UCSRnC.UMSELn | USARTn.CTRLC.CMODE[1:0](2) | USART Mode Select |
| UCSRnC.UPMn[1:0] | USARTn.CTRLC.PMODE[1:0] | Parity Mode |
| UCSRnC.UBSn | USARTn.CTRLC.SBMODE | Stop Bit Mode |
| UCSRnC.UCPOLn | USARTn.CTRLC.UCPHA(3) | Clock Polarity (SYNC MODE) |
| UBRRn[11:0] | USARTn.BAUD[15:0](4) | Baud Rate registers |
The following code snippets shows the initialization of the USART peripheral for both families:
#define USART_BAUDRATE 9600 #define BAUD_PRESCALE (((F_CPU / (USART_BAUDRATE * 16UL))) - 1)voidUSART_Init(void){/* Set baud rate */
UBRRL = BAUD_PRESCALE;/* Load lower 8 bits into the low byte of the UBRR register */
UBRRH =(BAUD_PRESCALE >>8);/* Load upper 8 bits into the high byte of the UBRR register */
UCSRB =(1<<RXEN)|(1<<TXEN);/* Enable receiver and transmitter */
UCSRC =(1<<USBS)|(3<<UCSZ0);/* Set frame format: 8data, 1 stop bit */}#define USART1_BAUD_RATE(BAUD_RATE) ((float)(64 * 4000000 / (16 * (float)BAUD_RATE)) + 0.5)voidUSART1_init(void){
USART1.BAUD =(uint16_t)(USART1_BAUD_RATE(9600));/* set the baud rate*/
USART1.CTRLC = USART_CHSIZE0_bm
| USART_CHSIZE1_bm;/* set the data format to 8-bit*/
USART1.CTRLB |= USART_RXEN_bm | USART_TXEN_bm;/* enable receiver and transmitter*/}