Each bank has a VDDI supply that powers the single-ended output drivers and the ratio input buffers such as LVTTL and LVCMOS. In addition to the bank VDDI supply, the GPIO banks include an auxiliary supply (VDDAUX) that powers the differential and referenced input buffers. Similarly, in HSIO banks, there are VDDI power pins, however, there are no dedicated VDDAUX pins as the VDD18 supply is used to power the differential and referenced input buffers. This flexibility of power supplies to the I/O provides independence for mixing I/O standards in the same bank.
PolarFire FPGA and PolarFire SoC FPGA inputs are designed to support mixing assignment for certain I/O standards, allowing I/O using compatible standards to be placed in the same I/O bank. The GPIO are self-protecting, which supports mixed input voltage combinations. It also supports over-voltage conditions because of its hot-swap design. For example, when VDDI is set to 3.3 V, a input receiver of 3.3 V, 2.5 V, 1.8 V, and 1.2 V. LVCMOS can be placed in the same I/O bank.
The mixing of different I/O within a bank is supported by the Libero SoC software. Before placing any mixed I/O voltage, you must first set the bank to the desired VDDI voltage followed by setting the attributes of the I/O that allows for mixed mode. Placing the I/O must be the last step. When implementing mixed I/O mode restrictions on ODT, CLAMP and RES_PULL must be followed. The HSIO receivers have a reduced set of compatible I/O standards because the I/O clamp-diode is set to ON. For GPIO, if the signaling levels of the receiver are greater than the VDDI of the bank, the clamp must be set to OFF. See the following tables for details on valid attributes.
The following tables list VDDI and mixed receiver compatibility for GPIO, HSIO for single-ended, reference and differential inputs. The tables list that inputs can be mixed within specific banks and still meet the I/O standards VIH/VIL requirements independent of the VDDI applied to the banks.
VDDI | LVTTL/LVCMOS33 | LVCMOS25 | LVCMOS18 | LVCMOS15 | LVCMOS12 |
---|---|---|---|---|---|
3.3 V | Yes | Yes2 | Yes2 | No | Yes2 |
2.5 V | Yes | Yes | Yes | Yes | Yes |
1.8 V | Yes | Yes | Yes | Yes | Yes |
1.5 V | Yes | Yes | Yes | Yes | Yes |
1.2 V | Yes | Yes | No | Yes | Yes |
(1) RES_PULL must be DOWN or NONE. All mixed modes above require CLAMP = OFF. (2) ODT must be OFF. |
Table 1 lists the compatible I/O types when mixing within the VDDI banks. Using the table for example, a VDDI low voltage of 1.2 V in GPIO can include LVCMOS33 inputs. Similarly, a VDDI low voltage of 1.2 V cannot include LVCMOS18 inputs.
VDDI | LVCMOS18 | LVCMOS15 | LVCMOS12 |
---|---|---|---|
1.8 V | Yes | Yes | Yes |
1.5 V | No | Yes | Yes |
1.35 V | No | No | Yes |
1.2 V | No | No | Yes |
(1) RES_PULL must be DOWN or NONE. All mixed modes above require CLAMP = ON. |
The following table lists GPIO mixed reference receiver mode data.
VDDI | VDDAUX | SSTL25 | SSTL18, HSUL18 | SSTL15, HSTL15 |
---|---|---|---|---|
3.3 V | 3.3 V | No | No | No |
2.5 V | 2.5 V | Yes (mid-range Vcm) | Yes (mid-range Vcm) | Yes (Low-range Vcm) |
1.8 V | 2.5 V | Yes (mid-range Vcm and clamp diode off) | Yes (mid-range Vcm) | Yes (Low-range Vcm) |
1.5 V | 2.5 V | Yes (mid-range Vcm and clamp diode off) | Yes (mid-range Vcm and clamp diode off) | Yes (Low-range Vcm) |
1.2 V | 2.5 V | No | No | No |
(1) ODT must be OFF for all cases. |
VDDI | SSTL15 HSUL15 |
SSTL18 HSTL18 |
SSTL135 HSTL135 |
HSUL12 HSTL12 POD |
---|---|---|---|---|
1.8 V | Yes (mid-range Vcm) |
Yes (mid-range Vcm) |
Yes (mid-range Vcm) |
Yes (mid-range Vcm) |
1.5 V | Yes (mid-range Vcm) |
No | Yes (mid-range Vcm) |
Yes (mid-range Vcm) |
1.35 V | No | No | Yes (mid-range Vcm) |
Yes (mid-range Vcm) |
1.2 V | No | No | No | Yes (mid-range Vcm) |
(1) ODT must be OFF for all cases. |
VDDI | LVDS25, RSDS25, SUBLVDS25, MINILVDS25, PPDS25, LCMDS25, SLVS25, HCSL25 | MIPI25 |
---|---|---|
3.3 V | No | Yes (Clamp diode ON or OFF) |
2.5 V | Yes | Yes |
1.8 V | Yes | Yes |
1.5 V | Yes | Yes |
1.2 V | Yes | Yes |
HSIO differential receivers do not support mixed I/O voltage combinations.