High-Speed Transceiver Logic (HSTL)

HSTL is a general-purpose, high-speed bus standard (EIA/JESD8-6) with a signaling range between 0 V and 1.5 V, and signals can either be single-ended or differential. This standard is used in memory bus interfaces with data switching capabilities of up to 1.267 GHz.

Following are the HSTL operational modes supported:

HSTL15I—HSTL Class I-standard with VDDI (nominal) = 1.5 V
HSTL15II—HSTL Class II-standard with VDDI (nominal) = 1.5 V
HSTL135I—HSTL Class I-standard with VDDI (nominal) = 1.35 V
HSTL135II—HSTL Class II-standard with VDDI (nominal) = 1.35 V
HSTL12I—HSTL Class I-standard with VDDI (nominal) = 1.2 V
HSTL12I—HSTL Class II-standard with VDDI (nominal) = 1.2 V

For more information about signal levels for the various HSTL I/O standards, see Table 1. Also, see respective PolarFire FPGA Datasheet or PolarFire SoC Advance Datasheet.

Note: HSTL135 and HSTL12 are not part of the JEDEC specification. They are scaled from HSTL15. For more information about HSTL signal levels, see respective PolarFire FPGA Datasheetor PolarFire SoC Advance Datasresheet.