Stub Series Terminated Logic (SSTL)

SSTL is a general-purpose memory bus standard. Following are the SSTL operational modes supported:

SSTL25 is defined by the JEDEC standard, JESD8-9B, and used for DDR SDRAM and DDR1 memory interfaces. SSTL18 is defined by the JEDEC standard, JESD8, and used for DDR2 SDRAM memory interfaces. SSTL15 is used for DDR3 memory interfaces; SSTL135 is used for DDR3L memory interfaces.

For more information about signal levels for the various SSTL I/O standards, see respective PolarFire FPGA Datasheet or PolarFire SoC Advance Datasheet.