HS_IO_CLK and System Clock Training

IOD interfaces implement Input gearing, de-serialization of the high-speed pad signals to lower speed parallel core signals, and the clock domain transfers, as required for the specific interface. The IOD implements a clock domain transfer for the data from the high-speed (HS_IO_CLK) to the low-speed system clock (SYSCLK) which is either GLOBAL or REGIONAL clock of the IOD macro. IOD Rx data is transferred from the Update Register (HS_IO_CLK domain) to the Transfer Register (SYSCLK) domain in the IGEAR logic. HS_IO_CLK and system clock training is implemented with interfaces where the data rate is greater than or equal to 400 Mbps, ratio 2, 3.5, 4. Interfaces using ratio x5 does not require HS_IO_CLK to system clock training because of its higher ratio which already provides adequate margin between them.

The Input IREG gearing logic data path uses three sets of registers to move the data between the domains. The following registers are depicted in Figure 1.

Figure 1. HS_IO_CLK to SYSCLK Data Transfer

Similarly, IOD Tx data is transferred from the Transfer Register (SYSCLK domain) to the Update Register (HS_IO_CLK domain) in the OGEAR logic using a same domain transfer topology.

Figure 2. SYSCLK to HS_IO_CLK Data Transfer

The HS_IO_CLK and SYSCLKs can have different insertion delays due to dissimilar routing paths within the fabric. This causes the rising clock edges to be misaligned potentially causing timing mismatches when the rising edges of these clocks are not aligned.

Figure 3. SYSCLK to HS_IO_CLK Before Training
Figure 4. SYSCLK to HS_IO_CLK After Training

In the Figure 3 and Figure 4, a PLL VCO phase adjustment for the HS_IO_CLK is required to align the rising edges of System clock and HS_IO_CLK for best performance. It requires use of the data EYE_MONITOR of an unused/spare IOD lane to derive the best setting. Upon completion, the CLK_TRAIN_DONE output indicates that the training is successful. CLK_TRAIN_ERROR indicates an error causing the HS_IO_CLK and system clock not to train. This can occur when the clocks are interrupted. CLK_TRAIN_ERROR is not available with fractional interfaces.