I/O Lanes in Each Bank

The following tables list the number of I/Os and lanes in each bank for each device and package option.

Table 1. PolarFire FPGA I/O Lanes in Each Bank

Devices

Packages

North Corner I/Os

 South Corner I/Os West Corner I/Os
Bank 0 Bank 7 Bank 1 Bank 3 Bank 2 Bank 6 Bank 4 Bank 5
HSIO Lanes HSIO Lanes HSIO Lanes JTAG GPIO Lanes HSIO Lanes GPIO Lanes GPIO Lanes
MPF100 FCSG325 36 3 0 0 48 4 13 48 4 0 0 38 3 0 0
MPF200 FCSG325_14.5x11 36 3 0 0 48 4 13 48 4 0 0 38 3 0 0
MPF200 FCSG536 60 5 0 0 60 5 13 96 8 0 0 84 7 0 0
MPF300 FCSG536 60 5 0 0 60 5 13 96 8 0 0 84 7 0 0
MPF100 FCVG484 60 5 0 0 60 5 13 96 8 0 0 68 5 0 0
MPF200 FCVG484 60 5 0 0 60 5 13 96 8 0 0 68 5 0 0
MPF300 FCVG484 60 5 0 0 60 5 13 96 8 0 0 68 5 0 0
MPF100 FCG484 48 4 0 0 48 4 13 84 7 0 0 64 5 0 0
MPF200 FCG484 48 4 0 0 48 4 13 84 7 0 0 64 5 0 0
MPF300 FCG484 48 4 0 0 48 4 13 84 7 0 0 64 5 0 0
MPF200 FCG784 72 6 24 2 60 5 13 96 8 0 0 92 7 44 3
MPF300 FCG784 72 6 24 2 60 5 13 96 8 0 0 92 7 44 3
MPF500 FCG784 72 6 24 2 60 5 13 96 8 0 0 92 7 44 3
MPF300 FCG1152 72 6 72 6 60 5 13 96 8 72 6 92 7 48 4
MPF500 FCG1152 72 6 96 8 60 5 13 96 8 96 8 92 7 72 6
Table 2. PolarFire SoC FPGA I/O Lanes in Each Bank

Devices

Packages

North Corner I/Os

 South Corner I/Os West Corner I/Os
Bank 0 Bank 7 Bank 1 Bank 3 Bank 2 Bank 6 Bank 4 Bank 5
HSIO Lanes HSIO Lanes HSIO Lanes JTAG GPIO Lanes HSIO Lanes GPIO Lanes GPIO Lanes
MPFS250 FCVG484 60 5 0 0 44 10 14 24 0 0 84 7 13 0 0
MPFS250 FCG1152 120 10 60 5 44 10 14 24 60 5 72 6 13 96 8
Note: Connectivity restrictions apply to the lanes listed as follows with regard to IOCDR and any IOD generic Rx interfaces using regional clock. This also implies a design cannot migrate from the MPF300, which has complete regional clock connectivity to the other devices with the listed impacted lanes.

The impacted lanes are as follows (as documented in the associated Package Pin Assignment Table (PPAT)):

MPF100, MPF200: DDR_S_3 (Bank 2, Lane 3)
MPF500: DDR_S_6 (Bank 2, Lane 6), DDR_N_9 (Bank 7, Lane 9)

Full duplex 1GbE and SGMII IOCDR are supported in the GPIO banks and permit only one per lane. See Full Duplex 1GbE and SGMII IOCDR.

Parent topic: I/O Lanes