Regional Clock Networks

The regional clock networks are low-latency networks. They can only distribute clocks to a certain area of the device with low skew. They can be driven from the divided CDR clock and the divided high-speed IO clock. PolarFire FPGAs and PolarFire SoC FPGAs offer one regional clock buffer per I/O lane on the northern, southern, and western edges. The size of the region depends on the regional clock buffer location and does not overlap. For more information about regional lock buffer location, see see PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide.