Input FIFO

After sampling valid DDR data, the positive and negative edge data needs to cross clock domains between the external synchronizing signal (for example, DQS for DDR memory controllers) and the internal system clock. The input FIFO also provides certainty of data being received at the FPGA with slightly different arrival times.

The input FIFO for each I/O is composed of two 8 flip-flop deep registers. One register is used for the input data associated with positive edge of clock and the other register is used for the input data associated with the negative edge of the clock. Both registers run on the negative clock edge, by using a previous half cycle transfer to put DDR input data all on one clock edge. There is a 3-bit write pointer and a 3-bit wide read pointer. The FIFO is used for clock domain transfers. For more information about Input FIFO, see I/O FIFO.