MIPI D-PHY Receive Interface

GPIO supports unidirectional MIPI D-PHY I/O in the receive direction, as shown in the following illustration. The MIPI D-PHY receiver supports high-speed (HS) signaling mode for data traffic and low-power (LP) signaling mode used for control. Each HS lane using MIPI25 is terminated and driven by a low-swing, differential signal. LP lanes operate single-ended and not terminated using two MIPI25 outputs driving each connection of the lane independently.

The MIPI receiver supports both the high-speed (HS) and a low-power (LP) receiver modes. These modes are selectable via an enable (HS_SEL) from the IOD component when MIPI low-power escape support is selected in the IOD Generic Receive Interfaces configurator (See Figure 1).

When the MIPI25 low-power escape support is used, the I/O is generated with a differential receiver between PADP and PADN. An additional single-ended receiver is connected to the PADP, allowing the HS_SEL signal to select between receivers. It also enables the 100 Ω differential termination resistor when HS_SEL = 1. This is generated by Libero SoC when selected in the IOD configurator.

When HS_SEL is selected, the HS_SEL pin serves as the output enable. When HS_SEL = 1, then the HS differential receiver and differential 100 Ω termination is turned ON and a single-ended receiver connected to the compliment PADN pin. When HS_SEL = 0, the differential termination is disabled and the single-ended receiver is enabled on the PADN pins. This MIPI interface is implemented by configuring PADP as a MIPI receiver, PADN pin and LVCMOS12 receiver. FPGA hosted logic is required to control this feature.

Figure 1. MIPI D-PHY Receiver
Note: Low-power LVMOS12 inputs are powered by internal VDD core. VDDI is not used with Low-power LVCMOS12 inputs.