External VREF Input

Any GPIO or HSIO pad on the device can be programmed to act as an external VREF input to supply all inputs within a bank. When an I/O pad is configured as a voltage reference, all I/O buffer modes and terminations on that pad are disabled. External VREF is supported for both GPIO and HSIO banks. By default, Libero SoC uses the internal VREF.

Use PDC or the I/O Attribute editor to choose any regular I/O to make it a VREF pin.

This is an example of a PDC command:

set_iobank -bank_name Bank0 \
-vcci 1.80 \
-vref 0.90 \
-vref_pins { U5 } \
-fixed false
set_iobank -bank_name Bank2 \
-vcci 1.80 \
-vref 0.90 \
-vref_pins { A2 } \
-fixed false
Note: When external VREF is used, the voltage on VREF pins can be any value between 0 and VDDI. However, the value of the -VREF attribute is specified in PDC as 50% of VDDI value.

Any available package pin can be selected and set it as a VREF. This requires placement of at least one I/O type requiring a VREF in IOeditor or pdc.

For more information about external reference inputs, see respective UG0726: PolarFire FPGA Board Design User Guide or PolarFire SoC FPGA Board Design Guidelines User Guide.