7:1 LVDS Transmit Interface

The transmit block uses double data rate registers of the TX_DDRX_B_A_X3.5 to transmit data on both the rising and falling edges of the clock. It multiplies the parallel clock by 3.5 and uses the clock to transmit seven serial bits of data in one parallel clock cycle and serialize the data into a single LVDS data stream. HS_IO_PAUSE needs to be pulsed after the clocks are stable. This forces all gearbox to be framed in the same cycle (including the one used to generate the clk). This assures synchronization of the data word. Word starts with the rising edge of the forwarded fractional clock.

Figure 1. TX_DDRX_B_A_X3.5