I/O Interface Timing Constraints

Libero SoC is capable of generating SDC timing constraints for design components used in IOD interfaces. These derived SDC constraints are based on the configuration of the IOD blocks including the sub-blocks required for the specific IOD functionality. The derived SDC constraints are placed in the <root>_derived_constraints.sdc file.

For static IOD Rx and Tx interfaces, static timing analysis can be done using the auto-generated derived constraints. Dynamic IOD Rx interfaces use a training operation on hardware to adapt the I/O timing to the PCB characteristics. For this capability, the derived SDC uses a wider range of delay and cannot be used to accurately perform timing analysis of external setup/hold timing of IOD generic Rx when configured in dynamic mode.