Dynamic Delay Control

Dynamic receiver delay controls are exposed on the IOD component by enabling it in the IOD configurator. On the IOD configurator -> Advanced (tab) -> Debug (pane), select the Expose dynamic delay control checkbox to add ports as shown in Figure 2. These ports are automatically exposed when selecting any of the RX_DDRX_DYNAMIC interfaces.

Table 1. Dynamic Delay Control Ports
Port I/O Description
DELAY_LINE_MOVE Input Change delay setting on rising edge
DELAY_LINE_DIRECTION Input Direction of delay setting change
DELAY_LINE_LOAD Input Asyn. Reload flash settings for delay
RANGE Output Delay setting has reached max or min range.

The delay_line_load signal asynchronously reloads the initial static flash bit delay settings.

The delay_line_move signal is a pulse and changes the delay setting by ±1 increment each time it is pulsed according to the delay_line_direction signal value.

“1” increases up the delay setting by one increment

“0” decreases down the delay setting by one increment

When the delay setting reaches the minimum value or the maximum value of the delay chain, the delay chain controller generates an delay_line_out_of_range output to indicate that it has reached the end of the delay chain. The delay setting stops at this min or max setting, even if the delay_line_move signal is still pulsing.

EYE_MONITOR_EARLY[n:0] Output The EYE_MONITOR_EARLY asserts if the data edge is close to the clock edge on the early side of clock. This flag indicates that the delay settings must be moved down.
EYE_MONITOR_LATE[n:0] Output The EYE_MONITOR_LATE asserts if the data edge is close to the clock edge on the late side of clock. This flag indicates that the delay setting must be moved up.
FLAGS[n:0] Input Use the EYE_MONITOR_CLEAR_FLAGS input signal to clear the “early” and “late” flags. This signal is from the fabric and indicates that the delay chain settings is incremented or decremented as a function of the previous flag settings.
EYE_MONITOR_WIDTH[2:0] Input Use the input signals “EYE_MONITOR_WIDTH<2:0>” to programably set a minimum delay space requirement between the data edges and the clock edges. The programmable delay settings are programmed in delay increments of 1, 2, 3, 4, 5, 6, or 8. This delay setting is between the clock edge and the data edge. This delay setting is then used to generate flags if the data edges are closer to the clock edges than the minimum setting. By allowing these signals to be dynamically controlled from the core, you can determine the relative size of the eye opening.