RX_DDRX_B_G_C and RX_DDRX_B_G_A/RX_DDRX_B_R_A Interfaces with Static Delays

RX_DDR interfaces can use x2, x3.5, x4, and x5 gearing using bank and lane oriented, high-speed I/O clock networks that provide low-skew, clocks distributed along the edge of the device to service the I/Os. Used to clock data into the I/O logic when implementing the I/O interfaces, the clocks are tightly managed to support wide source synchronous interfaces. The clock domain transfer for the data from the high-speed IO clock to the low-speed system clock is guaranteed by design. These modes permit wider data transfers to the fabric hence achieving more data throughput with lower fabric clock transfers.

The RX_DDRX[2,3.5,4,5]B_G_A/_B_R_A and RX_DDRX[2,3.5,4,5]B_G_C interfaces are also supported by static settings when the user is aware of the input and clock relationship at the boundary of the device. Similar to the RX_DDRX1 interfaces, the Libero SoC IOD configurator creates a component that meets the gearing criteria and is correct by construction from the pads to the fabric interface making use of the correct input pins required for clock and data. For each high-speed input receiver, the component is generated with the appropriate fabric pins based on the gearing ratio. For example, if a single high-speed input is intended to be geared by 4, then the component has 8 pins. The 8-pins has a relative pin name LN0_RXD_DATA[7:0] where as [0:1], [2:3], [4:5], [6:7] are the DDR equivalent for x4 geared data to the fabric.

Figure 1. Rx_geared Waveform