3.3 V Tolerant Input

As the demand to consolidate power supplies to lower power-supply voltages, bus translators are often necessary to interface between separately powered components of a logic system. However, the GPIO can operate as an LVCMOS25 input (VDDI = 2.5 V) and reliably receive a 3.3 V input signal. This is done by adding a 250 Ω series resistor and configuring the LVCMOS25 input with the CLAMP=OFF. This configuration is suitable for up to 50 MHz. Users must perform IBIS simulations to verify proper performance.