IOD Generic RX

The following table lists the receive interface software names and their related data.

Table 1. Receive Interface
Software Name Ratio Clock to Data Relationship I/O Clock Fabric Clock Lane Organi
zation One Lane Max Dynamic Bit Training
RX_DDR_G_A 1 Aligned Global Global
RX_DDR_R_A 1 Aligned Regional Regional
RX_DDR_G_C 1 Centered Global Global
RX_DDR_R_C 1 Centered Regional Regional
RX_DDRX_B_G_A 2, 3.5, 4, 5 Aligned High-speed I/O Clock Global
RX_DDRX_B_R_A 2, 3.5, 4, 5 Aligned High-speed I/O Clock Regional
RX_DDRX_B_G_C 2, 3.5, 4, 5 Centered High-speed I/O Clock Global
RX_DDRX_B_R_C 2, 3.5, 4, 5 Centered High-speed I/O Clock Regional
RX_DDRX_B_G_FA 2, 3.5, 4, 5 Fractional Aligned High-speed I/O Clock Global
RX_DDRX_B_G_
DYN 2, 3.5, 4, 5 Dynamic High-speed I/O Clock Global
RX_DDRX_B_R_
DYN 2, 3.5, 4, 5 Dynamic High-speed I/O Clock Regional

The following figure shows the IOD Generic Receive Interfaces.

Figure 1. IOD Generic Receive Interfaces—Configuration Tab
Table 2. IOD Generic Receive Interfaces—Configuration Tab
GUI Option Selections
Data rate User Input1
Number of data I/Os User Input – Number of desired RX data inputs (1 to 128)
Clock to data relationship Aligned, Centered, Dynamic, Fractional-aligned, and Fractional-dynamic2
Differential clock inputs Disable (single-ended) and Enabled (differential)
Differential data inputs Disable (single-ended) and Enabled (differential)
MIPI low power escape support Disable and Enable
Fabric Clock Ratio 1, 2, 3.5, 4, 5
Data deserialization ratio Predefined ports to the fabric from IOD component
Fabric clock source Fabric regional clock

Fabric global clock

Enable BITSLIP port Disable and Enable

Exposes BITSLIP pin when enabled. See Bit Slip for more information about Bit Slip. Not available for 3.5 Fabric clock ratio.

(1) See Receiver Interface (right panel) for valid data rates (Figure 1).  
Figure 2. IOD Generic Receive Interfaces—Advanced Tab
Table 3. IOD Generic Receive Interfaces—Advanced Tab
GUI Option Selections
Fabric global clock for external source Disable and Enable
Received data organization Received data spread over inputs, Received data independent over inputs, Received data spread over inputs with data/Control split.
RXD bus Width This allows organizing the splitting of the data bus.
RXCTL bus Width This allows organizing the splitting of the data bus.
Expose Rx raw data Disable and Enable. RXD_RAW_DATA ports are exposed on the module. Expose raw data is available for all fabric clock ratios except for ratio 5.
Expose fractional clock parallel data Disable and Enable. For fractional interfaces, RXD_CLK_DATA specifies the bit-slips needed to re-frame data.
Expose dynamic delay control Disable and Enable. See Table 1.
Add delay line on clock for RX_DDR_G_A/C Enables static delay chain to be added to clock path
Clock delay line tap Number of delay taps to be added. See Programmable I/O Delay section for information.
Enable RX_CLK_ODT_EN for LVDS failsafe See Dynamic ODT or Fail-Safe LVDS for information.
Enable RXD_ODT_EN for LVDS failsafe See Dynamic ODT or Fail-Safe LVDS for information.