IOD CDR Clocking

A dedicated CCC is generated by Libero SoC to support IOCDR interfaces. PF_IOD_CDR_CCC configurator provides the options to generate the module. The REF_CLK input is required based on the Data rate and CCC PLL clock multiplier. The PF_IOD_CDR_CCC does not allow divider control for the divider generating TX_CLK_G since the IOCDR only works in ratio 5 and is preset by Libero SoC. Libero SoC provides the proper timing constraints (as shown) when derived in the constraints manager.

create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV} -edges {1 7 11} -source [ get_pins { MY_DESIGN/PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/A } ] [ get_pins { MY_DESIGN/PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]