Generic IOD Interface Implementation

The I/O architecture includes many functional features to support source synchronous I/O interfaces such as DDR and QDR memory controllers, common interfaces such as RGMII, MIPI D-PHY, 7:1 LVDS, and several other non-memory user interfaces. Some interfaces such as memory interface solutions user soft-training IP to move data from the high-speed Bank I/O clock (HSIO_CLK) to the global clock of the interface.

The Libero SoC software offers many enhanced capabilities to streamline these interfaces easily into FPGA designs. The software is used to configure and generate all the high-speed interfaces such as IOD Generic RX and IOD Generic TX. The software generates a complete HDL module including clocking requirements for each of the interfaces. The Libero SoC built components are correct by construction containing the complete data path from the I/O pins to the fabric. Libero SoC software includes the following I/O interface configurators in the DirectCore catalog.

The following steps must be followed to successfully design a high-speed I/O gearing interface using Libero SoC software.

  1. 1.Determine the type of interface to implement for list of defined interfaces.
  2. 2.Use the I/O Interface configurators to build the interface.
  3. 3.Use available pre-sets within the I/O interface configurators for typical application interfaces
  4. 4.Add needed clock resources such as CCC.
  5. 5.Review package/device pin-out assignment tables for valid clock and data pins for each interface before making pin assignments. The smallest possible device/package combination that may be targeted to reduce architectural migration issues. Also review the Consolidated IOD Rules spreadsheet for pre-place and route guidance.
  6. 6.Confirm timing and clock constraints.
  7. 7.Define desired I/O standard for single-ended or differential I/O.