Enable Register

The following illustration shows enable register.

Figure 1. Enable Register

The following table lists the enable register pins and their descriptions.

Table 1. I/O Register Ports
Ports Types Descriptions
CLK Input Clock input
D Input Data input
Q Output Data output
LAT Input Latch enable (active high)
SD_B Input Synchronous data
AD_B Input Asynchronous data (active low)
Parent topic: I/O Registers