The PF_IOD_CDR interface provides an asynchronous receiver and a transmit interface for serial data transfers. This interface can support up to 1 GbE transfers. It supports serial protocols and other similar encoded serial protocols. PF_IOD_CDR uses a 10:1 digital ratio to provide a 10-bit data and clock interface for both transmit and receive modes. In the receive mode, the clock recovery circuit is used in the lane controller to generate the recovered clock. The PF_IOD_CDR interface is compatible with CoreTSE, CoreTSE_AHB, and CoreSGMII configured in TBI mode. For information about reference design using PF_IOD_CDR, see DG0799: PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Demo Guide.

The following illustration shows the PF_IOD_CDR transmit and receive interface.

Figure 1. PF_IOD_CDR Transmit and Receive Interface Modes

The IOD_CDR solutions requires two purposes built IP cores.

These two cores permit master and slave sharing. A BIF is available to connect the clock outputs from PF_IOD CDR CCC to PF_IOD CDR.

Figure 2. SmartDesign of IOD_CDR Topology