Programmable I/O Delay

The IOD block includes process, voltage, programmable delay chains for both input and output data paths. The input delay path has an intrinsic delay when the delay chain is enabled. This added delay is above the value of the incremental tap delay and is reported by the Libero SoC software when used. Consequently, there is a fast path to the fabric when the input delay chain is not present. The programmable delay chains on the output data path allow 128 tap delay. The enable path also includes a 8-tap programmable delay chain. The programmable delay chain can be set statically by using the I/O attribute editor or by using a PDC command in Libero SoC. The value per tap delay is not process, voltage, temperature(PVT) compensated and can have variation. For information about delays, see respective PolarFire FPGA Datasheet or PolarFire SoC Advance Datasheet.

The programmable delay chain is used to:

The programmable delay chain can also be controlled via dynamic control signals from the FPGA fabric. Dynamic delay control is useful for high-speed interfaces that require per-bit alignment.The dynamic control is only available for certain I/O interfaces, see Generic I/O Interfaces for more information. Static delay values can be controlled by PDC command constraint via IOEditor or manual constraint file input. In the PDC constraint file, IN_DELAY allows settings from OFF, 0-127, 128-254 (even numbers only).

example:

set_io -port_name PAD \
-IN_DELAY 2 \
-DIRECTION INPUT

The output delay values can be controlled by PDC command constraint via IOEditor or manual constraint file input. In the PDC constraint file, IN_DELAY allows settings from OFF, 1 - 128.

set_io -port_name PAD_0 \
-OUT_DELAY 2 \
-DIRECTION OUTPUT