Interface Ports

The following table lists the TX_DDR_G_A interface mode ports.

Table 1. TX_DDR_G/B_A Interface Mode Ports
Port I/O Description
TX_DATA[m:0] Input DDR transmit data from fabric. ‘m’ equals the input pins to the DDR component from the fabric where the even numbered pin is the data transmitted on the falling edge of TX_CLK and the odd numbered pin is the data transmitted on the rising of TX_CLK of the DDR signal. The number of fabric pins are based on the number of I/Os and the gearing ratio.
TX_CLK_G Input DDR transmit clock from fabric, and routed through global clock network.
TXD/TXD_N(m) Output DDR output to IOAs
TX_CLK Input DDR clock to IOAs
HS_IO_CLK_PAUSE Input Toggling the HS_IO_PAUSE. Resets the IOD TX state machines. This reset synchronizes HS_IO_CLK and TXCLK. It takes 5 to 10 clock cycles after deassertion of HS_IO_CLK_PAUSE until valid TX_DATA is accepted by the IOD.
(1) Other pins are visible when advanced options are used. See Generic IOD Interface Implementation.