Programmable Output Drive Strength

For LVCMOS, LVTTL, LVDS, and PPDS I/O standards, the I/O output buffer has programmable drive strength control to mitigate the effects of high-signal attenuation caused by long transmission lines.

The following table lists the programmable drive strength support and settings.

Table 1. Programmable Drive Strength Control
I/O Standards Supported I/O Types Drive Strength Settings (mA)
LVTTL GPIO (output only) 2, 4, 8, 12, 16, 20
LVCMOS33 GPIO (output only) 2, 4, 8, 12, 16, 20
LVCMOS25 GPIO (output only) 2, 4, 6, 8, 12, 16
LVDS25 and LVDS33 GPIO (output only) 3, 3.5, 4, 61
RSDS33 and RSDS25 GPIO (output only) 1.5, 2, 3
MINILVDS33 and MINILVDS25 GPIO (output only) 3, 3.5, 4, 6
SUBLVDS33 and SUBLVDS25 GPIO (output only) 1, 1.5, 2
PPDS33 and PPDS25 GPIO (output only) 1.5, 2, 3
LVCMOS18 GPIO and HSIO (output only) 2, 4, 6, 8, 10, 12
LVCMOS15 GPIO and HSIO (output only) 2, 4, 6, 8, 10
LVCMOS122 GPIO and HSIO (output only) 2, 4, 6, 8, 10
(1) Recommendation to use 100 Ω source termination with 6 mA LVDS output drive strength, that is, SOURCE_TERM = 100 when OUT_DRIVE = 6.

(2) LVCMOS12 output drive strength of 10 mA is supported only for HSIO.

 

The programmable drive strength is set by using the I/O attribute editor in Libero SoC or by using the following PDC command:

set_io –out_drive <value>

Values can be set as listed in Table 1.