Generic I/O Interfaces

Many pre-defined interfaces are available from the Libero SoC I/O configurator. You can select an interface from the list that closest matches their needs. See Generic IOD Interface Implementation for more information about software supported configurations. Based on targeted data rate, configurations use static settings that determine the clock or data relationships fixed by Libero SoC programming of delay elements within the IOD. Dynamic configuration uses dedicated logic controlled by fabric-based training IP that samples and adjusts internal timing elements to optimize the clock to data relationships. See Dynamic IOD Interface Training.

When building generic high-speed DDR interfaces, it is required to follow the Interface Rules described for each type of interface. The I/O supports a number of interface modes that can be selected to build the required data interface. The Package Pin Assignment Tables (PPAT) for device and package combination is available. The PPAT is used as a reference to select the proper pins with connectivity for the required resources needed for the interface. You must also be aware of performance specifications for IOA types when building their particular I/O interface. Select an I/O type that matches the desired maximum performance rate by referencing the respective PolarFire FPGA Datasheet or PolarFire SoC Advance Datasheet.

I/O blocks are used to construct dedicated memory interfaces. These interfaces are generated by Libero SoC using dedicated memory interface configurators for LPDDR3, DDR3, and DDR4 interfaces.