Interface Ports

The following table lists the port names and description of fractional aligned interface mode.

Table 1. Fractional Aligned Interface Mode Ports
Port I/O Description
RX Input Input DDR data. Supports up to 11 bits wide and all bits must fit within a lane.
RX_CLK Input Input DDR clock.
ARST_N Input Asynchronous reset to IOD and lane controller. ARST_N inputs are independent asynchronous resets to both the Rx and Tx IOD blocks. It holds associated interface PLLs in powerdown.
HS_IO_CLK_PAUSE Input Toggling the HS_IO_PAUSE:

– Resets the IOD RX state machines. This reset re-synchronizes pattern to HS_IO_CLK (bank clock) and RXCLK.

– Resets any adjustment done through SLIP operation.

– Resets the IOD TX state machines. This reset synchronizes HS_IO_CLK and TXCLK.

L#_RX_DATA[m:0] Output DDR output to FPGA fabric. ‘m’ equals the output pins from the geared DDR component to the fabric where the even numbered pin is the rising edge data and the odd numbered pin is the falling edge data of the DDR signal. The number of fabric pins are based on the number of I/Os and the gearing ratio. L# is associated with the # of external input pins up to 128 maximum.
RX_CLK_R/RX_CLK_G Output Receive clock to FPGA fabric using a global (G) or regional (R) clock.
PLL_LOCK Output Lock status of the included PLL used in clock path.
CLK_TRAIN_DONE Output Indicates HS_IO_CLK and system clock training is complete. See HS_IO_CLK and System Clock Training.