I/O Lanes

To support memory interfaces, I/O pairs are grouped into lanes, with multiple lanes per bank. Each lane consists of twelve I/Os (six I/O pairs), a lane controller, and a set of high-speed, low-skew clock resources. The uppermost lane on the western side of devices has less than six I/O pairs in each lane. The high-speed and low-skew clock resources in the I/O lane include a global clock network, regional clock networks, high-speed clock networks, and lane controller clock networks, see PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide for more information.

The I/O lane is used for easy implementation of integrated PHY for memory. For example, a 32-bit SDRAM interface requires four I/O data lanes. Each data lane uses one I/O lane—two I/O pads are used for DQS, eight I/O pads are used for DQ bits, one pad is used for data mask (DM), and one I/O pad is used as a spare. The lane topology is also used to construct generic I/O interfaces, which requires high-speed and low-skew clocking.

The following illustration shows the I/O lanes diagram.

Figure 1. I/O Lanes

Regional and Global I/O clock performance varies around the periphery of the device. The Regional Clock maximum frequency is slower than the Global I/O clock. This is inherent to device design as the regional clock is meant to be utilized in close proximity to its source.