Supported I/O Standards

GPIO and HSIO have configurable high-performance I/O drivers and receivers, supporting a wide variety of I/O standards.

The following table lists the I/O standards supported in the receiver and transmitter modes, respectively.

Table 1. Supported I/O
I/O Standards Receiver/Transmitter Modes VDDI

(Nominal) Required

Bank Types Applications
Single-Ended Standards
PCI Receiver, Transmitter 3.3 V GPIO PC and embedded systems
LVTTL1 Receiver 3.3 V, 2.5 V, 1.8 V, 
1.5 V, 1.2 V GPIO General purpose
Transmitter 3.3 V    
LVCMOS331 Receiver 3.3 V, 2.5 V, 1.8 V, 
1.5 V, 1.2 V GPIO General purpose
Transmitter 3.3 V    
LVCMOS251 Receiver 3.3 V, 2.5 V, 1.8 V, 
1.5 V, 1.2 V GPIO General purpose
Transmitter 2.5 V    
LVCMOS181 Receiver 3.3 V, 2.5 V, 1.8 V, 
1.5 V, 1.2 V GPIO, HSIO General purpose
Transmitter 1.8 V    
LVCMOS151 Receiver 3.3 V, 2.5 V, 1.8 V, 
1.5 V, 1.2 V GPIO, HSIO General purpose
Transmitter 1.5 V    
LVCMOS121 Receiver 3.3 V, 2.5 V, 1.8 V, 
1.5 V, 1.2 V GPIO, HSIO General purpose
Transmitter 1.2 V    
SSTL25I, 
SSTL25II Receiver 2.5 V GPIO DDR12
Transmitter 2.5 V GPIO DDR12
SSTL18I,

SSTL18II

Receiver, Transmitter 1.8 V GPIO, HSIO DDR22/RLDRAM22
SSTL15I,

SSTL15II

Receiver, Transmitter 1.5 V GPIO, HSIO DDR3
SSTL135I,

SSTL135II

Receiver, Transmitter 1.35 V HSIO DDR3L
HSTL15I,

HSTL15II

Receiver, Transmitter 1.5 V GPIO, HSIO QDRII+
HSTL135I,

HSTL135II

Receiver, Transmitter 1.35 V HSIO RLDRAM32
HSTL12I Receiver, Transmitter 1.2 V HSIO QDRII+
HSUL18I,

HSUL18II

Receiver, Transmitter 1.8 V GPIO, HSIO LPDDR2
HSUL12I,

HSUL12II

Receiver, Transmitter 1.2 V HSIO LPDDR22, LPDDR3
POD12I,

POD12II

Receiver, Transmitter 1.2 V HSIO DDR4
Differential Standards
LVDS18G Receiver 1.8 V GPIO General purpose
Transmitter3 1.8 V GPIO General purpose
LVDS33 Receiver 3.3 V GPIO General purpose
Transmitter3 3.3 V GPIO General purpose
LVDS25 Receiver 2.5V GPIO General purpose
Transmitter3 2.5V GPIO General purpose
LVDS184, 5 Receiver 1.8 V HSIO General purpose
RSDS33 Receiver 3.3 V GPIO General purpose
Transmitter3 3.3 V GPIO General purpose
RSDS25 Receiver 2.5 V GPIO General purpose
Transmitter3 2.5 V GPIO General purpose
RSDS185 Receiver 1.8 V HSIO General purpose
MINILVDS33 Receiver 3.3 V GPIO General purpose
Transmitter3 3.3 V GPIO General purpose
MINILVDS25 Receiver 2.5V GPIO General purpose
Transmitter3 2.5V GPIO General purpose
MINILVDS185 Receiver 1.8 V HSIO General purpose
SUBLVDS33 Receiver 3.3 V GPIO General purpose
Transmitter3 3.3 V GPIO General purpose
SUBLVDS25 Receiver 2.5V GPIO General purpose
Transmitter3 2.5V GPIO General purpose
SUBLVDS185 Receiver 1.8 V HSIO General purpose
PPDS33 Receiver 3.3 V GPIO General purpose
Transmitter3 3.3 V GPIO General purpose
PPDS25 Receiver 2.5 V GPIO General purpose
Transmitter3 2.5 V GPIO General purpose
PPDS185 Receiver 1.8 V HSIO General purpose
SLVS33 Receiver 3.3 V GPIO General purpose
SLVS25 Receiver 2.5 V GPIO General purpose
SLVS18 Receiver 1.8 V HSIO General purpose
SLVSE156 Transmitter 1.5 V GPIO, HSIO General purpose
HCSL33 Receiver 3.3 V GPIO General purpose
HCSL25 Receiver 2.5 V GPIO General purpose
HCSL18 Receiver 1.8 V HSIO General purpose
BUSLVDSE256 Transmitter 2.5 V GPIO Multipoint backplane applications
MLVDSE256 Transmitter 2.5 V GPIO Multipoint backplane applications
LVPECL33 Receiver 3.3 V GPIO Video graphics and clock distribution
LVPECLE336 Transmitter 3.3 V GPIO Video graphics and clock distribution
MIPI25 Receiver 2.5 V GPIO Consumer mobile applications
MIPIE256 Transmitter 2.5 V GPIO Consumer mobile applications, High–speed Mode
(1) Certain I/O standards are designed to support flexible VDDI assignment, see Mixed I/O in VDDI Banks.

(2) This application is supported by the I/O Standard, however, PolarFire FPGA and PolarFire SoC FPGA offering does not include the specific memory controller solution.

(3) Buffers configured for these standards are true-differential transmitters that do not support bidirectional operations.

(4) For HSIO, native LVDS inputs are supported with a single external-differential termination 100 Ω resistor, and LVDS transmit outputs are not supported in HSIO banks.

(5) These standards require an external voltage reference (VREF) and require two single-ended drivers with biasing through external resistors.

(6) Buffers are configured as emulated-differential transmitters and also support bidirectional operations. However, they require an external board termination.