RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN

The RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN interface is used to capture differential DDR data using dynamic control. The clock and data relationship can be adjusted dynamically when the device receives the differential DDR data. The RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN interface uses the digital ratio of 2, 3.5, 4, and 5.

The interface receives the differential data RXD/RXD_N and the differential clock RX_CLK_P/RX_CLK_N via I/O and passed the data Lx_RXD_DATA and fabric clock (RX_CLK_FAB) to the fabric. The receive clock input (RX_CLK_P/RX_CLK_N) is passed through the lane controller to generate RX_CLK_FAB, which is driven by RCLKINT.

The following illustration shows the signal waveform of RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN interface when slip input is not used.

Figure 1. RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN Waveform

The following illustration shows the block diagram of RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN interface.

Figure 2. Block Diagram of the RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN Interface
Note: For information about connections between IOD block and user training IP, see Dynamic Delay Control.