Transmit Interface

The PF_IOD_CDR transmit interface converts the parallel data into a serial data stream using the IOD interface. It receives the parallel data TXD[9:0] and transmits it via the I/O ports such as TX_P and TX_N. The PF_IOD_CDR transmit interface uses the same PLL used in the receive interface. The transmit clock generated is connected to the pin TX_CLK_G of the PF_IOD_CDR. The source clock is connected to HS_IO_CLK_0.

The following table shows the PF_IOD_CDR interface associated ports.

Table 1. PF_IOD_CDR Interface Associated Ports
Port I/O BIF Description
HS_IO_CLK_01 Input CDR_
CLOCKS Bank clock with phase 0 is used for both receive and transmit interface. Frequency must be half the rate of the serial data input.
HS_IO_CLK_901 Input CDR_
CLOCKS Bank clock with phase 90 is used for the I/O clock recovery. Frequency must be half the rate of the serial data input.
HS_IO_CLK_1801 Input CDR_
CLOCKS Bank clock with phase 180 is used for the I/O clock recovery. Frequency must be half the rate of the serial data input.
HS_IO_CLK_2701 Input CDR_
CLOCKS Bank clock with phase 270 is used for the I/O clock recovery. Frequency must be half the rate of the serial data input.
PLL_LOCK Input CDR_
CLOCKS Lock signal from CCC-PLL.
HS_IO_CLK_PAUSE Input CDR_
CLOCKS Toggling the HS_IO_PAUSE:

– Resets the IOD RX state machines. This reset re-synchronizes pattern to HS_IO_CLK (bank clock) and RXCLK.

– Resets any adjustment done through SLIP operation.

– Resets the IOD TX state machines. This reset synchronizes HS_IO_CLK and TXCLK.

DLL_LOCK Input CDR_
CLOCKS Lock signal from CCC-DLL.
TX_CLK_G Input CDR_
CLOCKS Transmit clock from the Fabric.
DLL_DELAY_CODE[6:0]2 Input CDR_
CLOCKS Delay code bus input from DLL-CCC. DLL delay code for 90° phase of the data.
DLL_VALID_CODE Input CDR_
CLOCKS Delay code valid input from Master IO_CDR Lane.
CDR_START Input CDR_
CLOCKS Start signal from the Master IO_CDR Lane.
STREAM_START Input   High input indicates valid serial input stream. STREAM_START signals to the CDR locks to a valid incoming serial data stream. This signal should not be tied high. It should be controlled to go high to indicate the incoming data stream is valid. This is extremely important at start-up or power-up.
TX_DATA[9:0] Input   Transmit parallel data.
ODT_EN Input   On Die Termination Enable Input. Optional pin is used with LVDS Fail Safe operation. See Dynamic ODT or Fail-Safe LVDS for information.
RX_P Input Pad   Serial data input (P side).
RX_N Input Pad   Serial data input (N side).
RX_BIT_SLIP3 Input   This port is used to rotate the parallel data word from the IOD to match the proper alignment of the data per lane.
RST_N4 Input   Active asynchronous low reset input.
RX_CLK_R Output   Recovered clock for the fabric interface is divided by five from the HS_IO_CLK. This clock is routed using a regional clock.
RX_VAL Output   The CDR is locked to the incoming serial data after indication by STREAM_START that the incoming data is valid. When the IO_CDR locks to the data, indicated by RX_VAL going high, any disruptions of data stream will not cause RX_VAL to change.
TX_P Output Pad   Serial data output (P side).
TX_N Output Pad   Serial data output (N side).
(1) PLL takes any reference clock input frequency (default 125 MHz) and outputs 625 MHz clock with 0, 90, 180, and 270 degree shift on four outputs.

(2) DLL takes 625 MHz reference clock input from the PLL output in Clock Reference Mode and outputs delay code as quarter of the clock cycle. The delay code is used in calculating of fine tune delay of CDR clock phase.

(3) User optional pin enabling the BITSLIP exposes the Lx_BIT_SLIP.

(4) Resets the IOD block of the IOCDR. Does not reset DLL.

 
Table 2. Advanced Tab Options
GUI Option Selections
Jump Size Step Do not change default
Expose Diagnostic Ports When checked, ports expose. (see Table 3)
Flag Window Size Do not change default
Table 3. Advanced Diagnostic Ports
Port I/O Description
SELA_LANE[10:0] Output SELA/SELB bits [1:0] toggles when the internal CDR clock is switched from delay line A to B or vice versa. The other bits [9:0] can be disregarded for debug.
SELB_LANE[10:0] Output
EARLY_N Output EYE_MONITOR_EARLY and EYE_MONITOR_LATE flag outputs indicate if the data edges are closer to the clock edges than this minimum setting.
LATE_N Output

CDR_READY Output Output asserts when CDR is locked and stays high until reset.
SWITCH_LANE Output Ports toggle when there is a clock phase shift. Accompanying with EARLY/LATE flags, this indicates if the phase shift is increasing or decreasing the delay line when SWITCH_LANE output asserts. If both flags are high with SWITCH_LANE high, there is clock jitter and/or causing data errors.
CLR_FLAGS_N Output