The following conditions are applicable when assigning pins to the RX_DDRX_B_G_DYN/ RX_DDRX_B_R_DYN interface:
- Interface uses two ICB_CLKDIVDELAY and three HS_IO_CLK.
- RX_CLK input must be placed in an I/O with the CLKIN_z_w function in the same bank as other I/Os.
- RX and RX_CLK I/Os must be placed in the same bank (exception on device with bank7, I/Os can be either in both bank0 and bank7).
- One IOD per data I/Os.
- One IOA per data and clock I/Os.
- IOA from two different interfaces (TX/RX/DDR/QDR/OCTAL/CDR) cannot be placed in the same I/O lane.