Interface Ports

The following table lists the RX_DDR_[G:R]_A interface mode ports.

Table 1. RX_DDR Aligned Interface Mode Ports
Port	I/O	Description
RX	Input	Input DDR data. Supports up to 128-bits for _G interfaces and 11-bit for _R interfaces.
RX_CLK	Input	Input DDR clock.
L#_RX_DATA[n:0]	Output	DDR output to FPGA fabric. ‘n’ equals the output pins from the geared DDR component to the fabric where the even numbered pin is the rising edge data and the odd numbered pin is the falling edge data of the DDR signal. The number of fabric pins are based on the number of I/Os and the gearing ratio. L# is associated with the # of external input pins up to 128 maximum.
RX_CLK_R/ RX_CLK_G	Output	Receive clock to FPGA fabric using a global (G), regional (R) clock.
⁽¹⁾ Other pins are visible when advanced options are used. See Generic IOD Interface Implementation.