TX DDR Interfaces
The following table lists the clock-to-data conditions of TX DDR interfaces.
Table 1.
TX DDR Interfaces
Interface Name
Topology
Gearing Ratio
Clock-to-Data Condition
TX_DDR_G/B_A
TX DDR
1
From a global clock source, aligned clock, and data
TX_DDR_G/B_A
Interface Ports
Interface Selection Rules
Parent topic:
Generic I/O Interfaces