RX DDR Interfaces

The IOD block are assembled using a combination of modules—Delay, IREG or IGEAR, FIFO, Gearing, Lane Controller, and Soft Training IP (TIP, not built automatically by Libero SoC). The I/O makes a direct use of clock topologies around the perimeter of the I/O ring to build synchronous I/O interfaces including lane clocks and bank (HS_IO_CLKs) clocks, local, and global clocks.

Purpose built input capture circuitry uses DDR registers, which captures incoming data on both the rising and falling edges of the clock incoming clock. The RX DDR interfaces are constructed in several input widths and clocking variations using the Libero SoC I/O interface configurators.

In FPGA generic I/O interfaces, there are three types of external interface definitions—centered, aligned, and fractional-aligned. In a centered I/O interface—at the device input pins—the clock is centered in the data opening. In an aligned external interface—at the device pins—the clock and data transition are aligned or edge-on-edge. Fractional aligned IOD mode is used when the receive clock is a fraction of the data rate. Interfaces use either a static or dynamic optimization methods to achieve specific data rate targets. Static uses Libero SoC generated data and clock delay tunings. Using constraints, you can adjust the data delay of a static interface. Dynamic uses IOD capabilities to adapt the interface for optimal performance. Static interfaces are turn-key using Libero SoC whereas dynamic requires user integration to optimize the interface for maximum performance.

The clock source in both types of interfaces can be sourced for a global, regional, or lane clock. See see PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide for more information about clocking topologies.

The Generic I/O Interfaces use a naming convention as follows:

Direction_Gearing_Capture clock_Fabric clock_Clock to data relationship

TX (direction), DDR (gearing), R (regional), C (Centered) ==> TX_DDR_R_C

DDRX (direction), B (HS_IO_CLK), FA (Fractional Clock Aligned), DYN (Dynamic alignment), FDYN (Fractional Clock with dynamic alignment)

Both the device families include the following generic RX DDR interface types.

Table 1. Generic RX DDR Interfaces1, 2
Name Clock Type Gearing Ratio Description
RX_DDR_G_A Continuous 1 Rx DDR w/Global aligned
RX_DDR_R_A Continuous 1 Rx DDR w/Regional clock aligned
RX_DDR_G_C Continuous 1 Rx DDR w/Global centered
RX_DDR_R_C Continuous 1 Rx DDR w/Regional clock centered
RX_DDRX_B_G_A Continuous 2, 3.5, 4, 5 Rx DDR geared w/Bank aligned using Global clock
RX_DDRX_B_G_C Continuous 2, 3.5, 4, 5 Rx DDR geared w/Bank centered using Global clock
RX_DDRX_B_R_A Continuous 2, 3.5, 4, 5 Rx DDR geared w/Bank aligned using Regional clock
RX_DDRX_B_R_C Continuous 2, 3.5, 4, 5 Rx DDR geared w/Bank centered using Regional clock
(1) For more information about maximum operating frequency, see respective PolarFire FPGA Datasheet or PolarFire SoC Advance Datasheet.

(2) Regional clock interfaces use the generated HS_IO_CLK to capture the data and then transfer to the regional clock within the FPGA fabric.