I/O Register Combining

I/O register combining is supported on enable, input, and output of any I/O. This support is available using the set_i off command, which is included in a Compile Netlist Constraint (*.ndc) file and passed to the Libero SoC Compile engine for netlist optimization after synthesis.


set_ioff -port_name {portname} \
[-IN_REG true/1|false/0] \

[-OUT_REG true/1|false/0] \

[-EN_REG true/1|false/0]


I/O register combining is only permitted with one FF with an I/O. The FF needs to be connected to the I/O with a fanout of one. A bidirectional I/O where both D and Y pins are driven with registered signals can only allow one of the registers to be moved into the I/O pad.

There is another option to allow automatic I/O register combining. This option is enabled from the Place and Route configuration settings. Right-click Place and Route in the project navigator and select the I/O Register Combining checkbox. Enable this option to combine any register directly connected to an I/O when it has a timing Constraint. If there are multiple registers directly connected to a (bi-directional) I/O, select one register to combine in the following order: input-data, output-data, output-enable. Users can use the NDC constraint discussed above for more tightly controlling the use of I/O register combining.

Note: This feature is OFF by default. Users must turn it ON to enable combining.

Every I/O has several embedded registers that you can use for faster clock-to-out timing, and external hold and setup. When combining these registers at the I/O buffer, some design rules must be met.

This feature is supported by all I/O standards.

Following are the rules to combining the I/O registers:

Figure 1. I/O Register Combining from Place and Route Layout Options