RX_DDR Fractional Aligned/Fractional Dynamic Interfaces

The DDR fractional aligned IOD mode is used when the receive clock is a fraction of the data rate. A CCC PLL is inserted by Libero SoC into the clock path with a multiplier of 1, 2, 4, 8, or 10 to match data bit rate. For example, source synchronous clock input RX_CLK (which is data-rate / 4) is provided as a reference clock to a fabric PLL, and generates the HS_IO_CLK which is 2X the RX_CLK. With statically trained interface, the static delays to ensure the HS_IO_CLK clock edge alignment within the RXD data bit window. This pre-instantiated PLL also generates the fabric clock (equal to the RX_CLK or data-rate / 4), which is used by the user logic in the fabric to clock the RX_DATA bits coming out of the IOD macro into the fabric.

The following figures shows the waveform diagram of fractional aligned data and clock.

Figure 1. Fractional Aligned Data and Clock Waveform