High-Speed I/O Bank Clock Resource (HS_IO_CLK)

High-speed I/O bank clock networks are integrated into I/O banks and distribute clocks along the entire I/O bank with low-skew. They are used to clock data in and out of the I/O logic when implementing the high-speed interfaces. The high-speed I/O clock networks are located on the east corner of the FPGA fabric. Each I/O bank can have six high-speed I/O clocks. High-speed I/O clocks from adjacent banks on the same edge can be bridged to build large I/O interfaces. HS_IO_CLK bridging is allowed only for fractional IOD Rx interfaces (See RX_DDR Fractional Aligned/Fractional Dynamic Interfaces).

High-speed I/O clock networks are driven either from I/Os or CCCs. The high-speed clocks can be configured to feed reference clock inputs of adjacent CCCs. HS_IO_CLKs are transparent as they are setup by Libero SoC based on configuration.

Figure 1. Distribution of the HS_IO_CLK