Open Drain GPIO

GPIO can be used to create an open-drain output when VDDI is below the required high output level. In this case, the GPIO pin only drives a LOW output. When not driving LOW, it is externally pulled-up to a maximum of 3.45 V through an external pull-up resistor. This is accomplished by selecting the CLAMP = OFF and the internal RES_PULL = NONE. The FPGA design can connect the related output enable (E) and connect it to the inverted data signal.

Figure 1. Open Drain GPIO Example
Note: External pull-up values of 250 Ω are suggested up to 33 MHz operations. 200 Ω pull-up is suggested for up to 50 MHz. Users must perform IBIS simulations to verify proper performance.