Peripheral Overview

TIMER0

Timer0 can operate either as an 8-bit or 16-bit timer. The 16-bit mode is enabled by setting the T016BIT bit.

In the 8-bit mode, a buffered version of TMR0H is maintained. This is compared with the value of TMR0L on each cycle of the selected clock source. When the two values match, the following events occur:

TMR0L is reset
The contents of TMR0H are copied to the TMR0H buffer for next comparison

In the 16-bit mode, TMR0H:TMR0L form the 16-bit timer value and read and write of the TMR0H register are buffered. Timer0 rolls over to 0x0000 on incrementing past 0xFFFF. This makes the timer free-running. TMR0L/H registers cannot be reloaded in this mode once started. In both 8-bit and 16-bit modes, Timer0 increments on the rising edge of the selected clock source.

Figure 1. Timer0 Block Diagram

TIMER 1/3/5

Timer1 module is a 16-bit incrementing counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used either as a timer or counter and increments on every selected edge of the external source. Timer1 can function on several possible synchronous and asynchronous clock sources. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2-LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input.

Important: References to module Timer1 apply to all the odd numbered timers on this device.

Timer1 is a 16-bit module which has the following features:

16-Bit Timer/Counter register
Optionally synchronized comparator out
Multiple Timer1 gate (count enable) sources
Interrupt-on-Overflow
Wake-Up on Overflow (external clock, Asynchronous mode only)
Time base for the capture/compare function with the CCP modules
Special Event Trigger (with CCP)

The following figure is a simplified diagram showing signal flow through the TMR1.

Figure 2. Timer1 Block Diagram

TIMER 2/4/6

Timer2 operates in three major modes:

Free Running Period
One-shot
Monostable

Free-Running Period Mode

The value of T2TMR is compared to that of the Period register (T2PR) on each clock cycle. When the two values match, the comparator resets the value of T2TMR to 00h on the next cycle and increments the output postscaler counter. When the postscaler count equals the value in the OUTPS bits of the T2CON register, then a one clock period wide pulse occurs on the TMR2_postscaled output and the postscaler count is cleared.

One-Shot Mode

The One-Shot mode is identical to the Free-Running Period mode except for when the ON bit is cleared and the timer is stopped when T2TMR matches T2PR and will not restart until the ON bit is cycled off and on. The Postscaler (OUTPS) values other than zero are ignored in this mode because the timer is stopped at the first period event and the postscaler is reset when the timer is restarted.

Monostable Mode

Monostable modes are similar to One-Shot modes except for when the ON bit is not cleared and the timer can be restarted by an external Reset event.

Figure 3. Timer2 Block Diagram

Notes:

1.This signal comes from the pin selected by TxCKIPPS.
2.TMRx register increments on rising edge.
3.Synchronize does not operate while in Sleep.
4.See TMRxCLK for clock source selections from device data sheet.
5.See TMRxGATE for gate source selection from device data sheet.
6.Synchronized comparator output should not be used in conjunction with synchronized input clock.