INTENSET

Interrupt Enable Set

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
  0x04 32 PAC Write-Protection 0x00000000  
Parent topic: Register Description

Interrupt Enable Set

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
            CLKFAIL   XOSC32KRDY  
Access            R/W   R/W  
Reset            0   0  

Bit 2 – CLKFAIL: XOSC32K Clock Failure Detection Interrupt Enable

XOSC32K Clock Failure Detection Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the XOSC32K Clock Failure Interrupt Enable bit, which enables the XOSC32K Clock Failure interrupt.

ValueDescription
0 The XOSC32K Clock Failure Detection is disabled.
1 The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the XOSC32K Clock Failure Detection interrupt flag is set.

Bit 0 – XOSC32KRDY: XOSC32K Ready Interrupt Enable

XOSC32K Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready interrupt.

ValueDescription
0 The XOSC32K Ready interrupt is disabled.
1 The XOSC32K Ready interrupt is enabled.