AHB Mask
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
TRAM | Reserved | Reserved | Reserved | Reserved | |||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 1 | 1 | 1 | 1 | 1 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NVMCTRL | PAC | Reserved | DSU | DMAC | APBC | APBB | APBA | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
TRAM AHB Clock Enable
Value | Description |
---|---|
0 | The AHB clock for the TRAM is stopped |
1 | The AHB clock for the TRAM is enabled |
Must Be Set to 1
Must Be Set to 1
Must Be Set to 1
Must Be Set to 1
NVMCTRL AHB Clock Enable
Value | Description |
---|---|
0 | The AHB clock for the NVMCTRL is stopped |
1 | The AHB clock for the NVMCTRL is enabled |
PAC AHB Clock Enable
Value | Description |
---|---|
0 | The AHB clock for the PAC is stopped. |
1 | The AHB clock for the PAC is enabled. |
Must Be Set to 1
DSU AHB Clock Enable
Value | Description |
---|---|
0 | The AHB clock for the DSU is stopped. |
1 | The AHB clock for the DSU is enabled. |
DMAC AHB Clock Enable
Value | Description |
---|---|
0 | The AHB clock for the DMAC is stopped. |
1 | The AHB clock for the DMAC is enabled. |
AHB-APB Bridge C AHB Clock Enable
Value | Description |
---|---|
0 | The AHB clock for the APBC is stopped. |
1 | The AHB clock for the APBC is enabled |
AHB-APB Bridge B AHB Clock Enable
Value | Description |
---|---|
0 | The AHB clock for the APBB is stopped. |
1 | The AHB clock for the APBB is enabled. |
AHB-APB Bridge A AHB Clock Enable
Value | Description |
---|---|
0 | The AHB clock for the APBA is stopped. |
1 | The AHB clock for the APBA is enabled. |