APBAMASK

APBA Mask

  0x14 32 PAC Write-Protection 0x000007FFF  
Parent topic: Register Description

APBA Mask

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
    Reserved AC PORT FREQM EIC RTC WDT  
Access    R/W R/W R/W R/W R/W R/W R/W  
Reset    1 1 1 1 1 1 1  
Bit  7 6 5 4 3 2 1 0  
  GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  1 1 1 1 1 1 1 1  

Bit 13 – AC: AC APBA Clock Enable

AC APBA Clock Enable

ValueDescription
0 The APBA clock for the AC is stopped.
1 The APBA clock for the AC is enabled.

Bit 12 – PORT: PORT APBA Clock Enable

PORT APBA Clock Enable

ValueDescription
0 The APBA clock for the PORT is stopped.
1 The APBA clock for the PORT is enabled.

Bit 11 – FREQM: FREQM APBA Clock Enable

FREQM APBA Clock Enable

ValueDescription
0 The APBA clock for the FREQM is stopped.
1 The APBA clock for the FREQM is enabled.

Bit 10 – EIC: EIC APBA Clock Enable

EIC APBA Clock Enable

ValueDescription
0 The APBA clock for the EIC is stopped.
1 The APBA clock for the EIC is enabled.

Bit 9 – RTC: RTC APBA Clock Enable

RTC APBA Clock Enable

ValueDescription
0 The APBA clock for the RTC is stopped.
1 The APBA clock for the RTC is enabled.

Bit 8 – WDT: WDT APBA Clock Enable

WDT APBA Clock Enable

ValueDescription
0 The APBA clock for the WDT is stopped.
1 The APBA clock for the WDT is enabled.

Bit 7 – GCLK: GCLK APBA Clock Enable

GCLK APBA Clock Enable

ValueDescription
0 The APBA clock for the GCLK is stopped.
1 The APBA clock for the GCLK is enabled.

Bit 6 – SUPC: SUPC APBA Clock Enable

SUPC APBA Clock Enable

ValueDescription
0 The APBA clock for the SUPC is stopped.
1 The APBA clock for the SUPC is enabled.

Bit 5 – OSC32KCTRL: OSC32KCTRL APBA Clock Enable

OSC32KCTRL APBA Clock Enable

ValueDescription
0 The APBA clock for the OSC32KCTRL is stopped.
1 The APBA clock for the OSC32KCTRL is enabled.

Bit 4 – OSCCTRL: OSCCTRL APBA Clock Enable

OSCCTRL APBA Clock Enable

ValueDescription
0 The APBA clock for the OSCCTRL is stopped.
1 The APBA clock for the OSCCTRL is enabled.

Bit 3 – RSTC: RSTC APBA Clock Enable

RSTC APBA Clock Enable

ValueDescription
0 The APBA clock for the RSTC is stopped.
1 The APBA clock for the RSTC is enabled.

Bit 2 – MCLK: MCLK APBA Clock Enable

MCLK APBA Clock Enable

ValueDescription
0 The APBA clock for the MCLK is stopped.
1 The APBA clock for the MCLK is enabled.

Bit 1 – PM: PM APBA Clock Enable

PM APBA Clock Enable

ValueDescription
0 The APBA clock for the PM is stopped.
1 The APBA clock for the PM is enabled.

Bit 0 – PAC: PAC APBA Clock Enable

PAC APBA Clock Enable

ValueDescription
0 The APBA clock for the PAC is stopped.
1 The APBA clock for the PAC is enabled.

Bit 14 – Reserved: For future use

For future use

Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0.