This register allows the
user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register
(INTENSET).
|
0x60 |
32 |
PAC Write-Protection |
0x00000000 |
|
Non-Secure Check
Interrupt Enable
Writing '0' to this bit has no effect.
Writing '1' to this bit will clear the Non-Secure Check Interrupt
Enable bit, which disables the Non-Secure Check interrupt.
Value | Description |
---|
0 |
The
Non-Secure Check interrupt is disabled. |
1 |
The
Non-Secure Check interrupt is enabled. |