SYNCBUSY

Synchronization Busy in COUNT32 mode (CTRLA.MODE=0)

  0x10 32 - 0x00000000    
Parent topic: Register Description - Mode 0 - 32-Bit Counter

Synchronization Busy in COUNT32 mode (CTRLA.MODE=0)

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
              GP1 GP0  
Access              R R  
Reset              0 0  
Bit  15 14 13 12 11 10 9 8  
  COUNTSYNC                
Access  R                
Reset  0                
Bit  7 6 5 4 3 2 1 0  
      COMP0   COUNT FREQCORR ENABLE SWRST  
Access      R   R R R R  
Reset      0   0 0 0 0  

Bits 16, 17 – GPn: General Purpose n Synchronization Busy Status [n = 1..0]

General Purpose n Synchronization Busy Status [n = 1..0]

ValueDescription
0 Write synchronization for GPn register is complete.
1 Write synchronization for GPn register is ongoing.

Bit 15 – COUNTSYNC: Count Read Sync Enable Synchronization Busy Status

Count Read Sync Enable Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.COUNTSYNC bit is complete.
1 Write synchronization for CTRLA.COUNTSYNC bit is ongoing.

Bit 5 – COMP0: Compare 0 Synchronization Busy Status

Compare 0 Synchronization Busy Status

ValueDescription
0 Write synchronization for COMP0 register is complete.
1 Write synchronization for COMP0 register is ongoing.

Bit 3 – COUNT: Count Value Synchronization Busy Status

Count Value Synchronization Busy Status

ValueDescription
0 Read/write synchronization for COUNT register is complete.
1 Read/write synchronization for COUNT register is ongoing.

Bit 2 – FREQCORR: Frequency Correction Synchronization Busy Status

Frequency Correction Synchronization Busy Status

ValueDescription
0 Write synchronization for FREQCORR register is complete.
1 Write synchronization for FREQCORR register is ongoing.

Bit 1 – ENABLE: Enable Synchronization Busy Status

Enable Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.ENABLE bit is complete.
1 Write synchronization for CTRLA.ENABLE bit is ongoing.

Bit 0 – SWRST: Software Reset Synchronization Busy Status

Software Reset Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.SWRST bit is complete.
1 Write synchronization for CTRLA.SWRST bit is ongoing.