Power Domain Controller

The Power Domain Controller provides several ways of how power domains are handled while the device is in Standby mode or entering Standby mode:

Default operation - all peripherals idle
When entering Standby mode, the power domain PDSW is set in retention state. This allows for very low power consumption while retaining all the logic content of these power domains. When exiting Standby mode, all power domains are set back to active state.

Default operation - Standby Sleep Mode with static power gating
Static Power Domain Gating is a technique that allows to automatically turn off the PDSW power domain supply when not used while keeping PDAO powered up.

SleepWalking extension to power gating (SleepWalking with dynamic power gating)
SleepWalking is the capability for a device in Standby Sleep mode, to temporarily wake-up clocks for a peripheral to perform a task without waking-up the CPU. The SleepWalking feature has been expanded to control power gating in addition to clock gating. The power domain PDSW can be automatically controlled (active or retention state) depending on peripheral requirements (PDCFG bit from the STDBYCFG register).

The static and dynamic power gating features are fully transparent for the user.

Table 1. Sleep Modes versus Power Domain States Overview
	Power Domain State
Sleep Mode	PDSW	PDAO
Active	active	active
Idle	active	active
Standby - At least one peripheral from PDSW with RUNSTDBY = 1 OR PDCFG = 1	active ⁽¹⁾	active
Standby - No peripheral from PDSW with RUNSTDBY = 1	retention	active
Off	off	off

Note:

1.PDSW can be switched automatically in retention mode if the dynamic power gating feature is enabled.