DPLLCTRLB

DPLL Control B

  0x34 32 PAC Write-Protection 0x00000000  
Parent topic: Register Description

DPLL Control B

Bit  31 30 29 28 27 26 25 24  
            DIV[10:8]  
Access            R/W R/W R/W  
Reset            0 0 0  
Bit  23 22 21 20 19 18 17 16  
  DIV[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
        LBYPASS   LTIME[2:0]  
Access        R/W   R/W R/W R/W  
Reset        0   0 0 0  
Bit  7 6 5 4 3 2 1 0  
      REFCLK[1:0] WUF LPEN FILTER[1:0]  
Access      R/W R/W R/W R/W R/W R/W  
Reset      0 0 0 0 0 0  

Bits 26:16 – DIV[10:0]: Clock Divider

Clock Divider

These bits set the XOSC clock division factor and can be calculated with following formula:

fDIV=fXOSC2x(DIV+1)

Bit 12 – LBYPASS: Lock Bypass

Lock Bypass

ValueDescription
0 DPLL Lock signal drives the DPLL controller internal logic.
1 DPLL Lock signal is always asserted.

Bits 10:8 – LTIME[2:0]: Lock Time

Lock Time

These bits select the lock time-out value:

Note: GCLK_DPLL_32K is responsible for counting the user defined lock time (LTIME different from 0x0), hence must be enabled.
ValueNameDescription
0x0 Default No time-out. Automatic lock.
0x1 Reserved  
0x2 Reserved  
0x3 Reserved  
0x4 8MS Time-out if no lock within 8ms
0x5 9MS Time-out if no lock within 9ms
0x6 10MS Time-out if no lock within 10ms
0x7 11MS Time-out if no lock within 11ms

Bits 5:4 – REFCLK[1:0]: Reference Clock Selection

Reference Clock Selection

Write these bits to select the DPLL clock reference:

ValueNameDescription
0x0 XOSC32K XOSC32K clock reference
0x1 XOSC XOSC clock reference
0x2 GCLK GCLK_DPLL clock reference
0x3 Reserved -

Bit 3 – WUF: Wake Up Fast

Wake Up Fast

ValueDescription
0 DPLL clock is output after startup and lock time.
1 DPLL clock is output after startup time.

Bit 2 – LPEN: Low-Power Enable

Low-Power Enable

ValueDescription
0 The low-power mode is disabled. Time to Digital Converter is enabled.
1 The low-power mode is enabled. Time to Digital Converter is disabled. This will improve power consumption but increase the output jitter.

Bits 1:0 – FILTER[1:0]: Proportional Integral Filter Selection

Proportional Integral Filter Selection

These bits select the DPLL filter type:

ValueNameDescription
0x0 DEFAULT Default filter mode
0x1 LBFILT Low bandwidth filter
0x2 HBFILT High bandwidth filter
0x3 HDFILT High damping filter